1. 05 Mar, 2014 2 commits
  2. 19 Feb, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Pre-version 2.0 commit · 64f1a255
      Theodor-Adrian Stana authored
      Changes:
      
      HDL:
      
      - added pulse time tagging core (pulse_timetag.vhd)
      - added FIFO via the conv_regs.wb file
      - to make the FIFO read work properly, I needed to change the
      wb_i2c_bridge component (general-cores submodule)
      - updated top-level to connect the FIFO to conv_regs component
      - moved the pulse generator glitch filter to outside the pulse
      generator
      - changed the conv_pulse_gen block to be able to properly reject
      pulses up to only 1/5 duty cycle, not more (I realized by simulation
      that when the glitch filter was enabled, it needed one extra cycle,
      thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle)
      - updated synthesis files for the Release project to add the new files,
      and the regtest and pulsetest due to the I2C bridge changes
      
      Simulation files:
      - conv_pulse_gen: changes for the aforementioned change test
      - added pulse_timetag sim files
      - added release top-level simulation, which at the moment does
      not contain a lot of stuff (only pulse rep test), but can be used as a
      starter to verify the design works appropriately
      
      Doc:
      - updated memory map with cute wbgen-ized memory map
      - added time-tagging core information
      - updated the Getting Around the Code section
      - added and updated figures
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      64f1a255
  3. 05 Feb, 2014 1 commit
  4. 03 Feb, 2014 3 commits
    • Theodor-Adrian Stana's avatar
    • Theodor-Adrian Stana's avatar
      hdl: Fixed a problem with the pulse counters · 5dcc4b58
      Theodor-Adrian Stana authored
      When the TTL selection switch is set for TTL-BAR signals, the pulse counters
      were starting from the value 1. This was because the input channel is
      first sent through a synchronizer FF chain, which was reset by the
      same reset signal as the rest of the logic.
      
      Due to the reset pulse inside the logic and the fact that when the TTL switch
      is set to TTL-BAR, a non-existing signal represents a high level, this
      high level was detected (due to the sync FF chain) only after the reset pulse.
      This resulted in a rising edge on the trigger signal, which resulted in the
      pulse counters incrementing to '1' on every reset.
      
      This problem has been solved by not resetting the sync FF chain.
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      5dcc4b58
    • Theodor-Adrian Stana's avatar
      hdl: Made manual pulse triggering safer · a9306cba
      Theodor-Adrian Stana authored
      This was done by reading the whole value of the 8-bit MPT field
      after the magic sequence is input. Before, only the number of bits
      corresponding to the number of channels at the input was read, which
      could result in a pulse being generated when a wrong channel value with
      a "correct" mask is input to the field, as for example:
      
      - on the six-channel CONV-TTL-BLO, 0x9 in MPT gets masked on three bits to 0x1,
      thus a pulse is generated on CH1
      Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
      a9306cba
  5. 30 Jan, 2014 4 commits
  6. 29 Jan, 2014 1 commit
  7. 28 Jan, 2014 2 commits
  8. 27 Jan, 2014 1 commit
  9. 07 Jan, 2014 4 commits
  10. 05 Jan, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Updated HDL guide · 68e5ac71
      Theodor-Adrian Stana authored
      - made HDL block diagram clearer
      - updated architecture organization figure
      - updated folder structure
      - changed overall document organization, `Folder structure' and
      `Getting around the code sections' are now after `Introduction'
      - some small changes in text and wording
      Signed-off-by: Theodor-Adrian Stana's avatarThedi Stana <t.stana@cern.ch>
      68e5ac71
  11. 19 Dec, 2013 1 commit
  12. 08 Dec, 2013 6 commits
  13. 20 Nov, 2013 2 commits
  14. 19 Nov, 2013 5 commits
  15. 18 Nov, 2013 6 commits