Commented out the hack for v3 boards, where the PCB version is not yet available. the previous top file was enabling the burst mode via a dip switch sw2.3. In final release this functionality is ONLY enabled by reading the PCB version inputs to the FPGA

Renamed some of conv-common-gw ports to avoid references to signal types (ttl or blo) are yet to be changed. this is not a priority for release 4 of the gateware.

Doc: Updated hdl guide with additional note on inverter channel output LEDs. fixed a typo on conv-regs.

Small modification in p_inhibit_first_pulse process, now checks that all lines are low before end of 100us first pulse inhibit period.

UCF file adds some attributes to the input channel i/o to bypass the fact it is not a clock despite being used as a clock in the flancter

UCF file includes two extra pins for additional 2 bits identifying the pcb execution number. This is in addition to the 4 bits for the version number