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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
feac5e78
Commit
feac5e78
authored
Dec 07, 2016
by
Denia Bouhired-Ferrag
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added testbench file for burst controller module
parent
31465e65
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37 additions
and
15 deletions
+37
-15
burst_ctrl_tb.vhd
sim/Release/burst_ctrl_tb.vhd
+37
-15
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sim/Release/burst_ctrl_tb.vhd
View file @
feac5e78
...
...
@@ -91,8 +91,8 @@ architecture behav of testbench is
g_pwidth
:
natural
range
2
to
40
:
=
5
;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div
:
natural
:
=
18
;
g_1_pulse_energ
:
in
integer
:
=
10
;
g_max_temp_rise
:
in
integer
range
0
to
1000000
:
=
1000
g_1_pulse_energ
:
in
unsigned
(
15
downto
0
)
;
g_max_temp_rise
:
in
unsigned
(
39
downto
0
)
);
port
(
...
...
@@ -104,7 +104,7 @@ architecture behav of testbench is
en_i
:
in
std_logic
;
pulse_burst_i
:
in
std_logic
;
temp_rise_c
:
out
integer
;
temp_rise_c
:
out
unsigned
(
39
downto
0
)
;
pulse_burst_o
:
out
std_logic
;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
...
...
@@ -125,24 +125,27 @@ architecture behav of testbench is
--signal burst_train_dyn : std_logic;
signal
burst_train_regulated
:
std_logic
;
signal
burst_train_regulated_dyn
:
std_logic
;
signal
temp_rise_counter
:
integer
;
signal
temp_rise_counter
:
unsigned
(
39
downto
0
)
;
signal
rand_num
:
integer
:
=
0
;
signal
t_start
:
TIME
:
=
NOW
;
signal
t_sim1
:
TIME
:
=
0
ns
;
signal
t_sim2
:
TIME
:
=
0
ns
;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- ============================================================================
-- ===========================================================================
--Instantiate the DUT: Burst controller averaged over 1000 pulses
--============================================================================
cmp_dut_1
:
conv_burst_ctrl
generic
map
(
g_pwidth
=>
5
,
g_duty_cycle_div
=>
100
,
g_duty_cycle_div
=>
2
,
g_max_burst_len
=>
3
,
g_burst_timeout
=>
50000
)
...
...
@@ -167,8 +170,10 @@ architecture behav of testbench is
(
g_pwidth
=>
5
,
g_duty_cycle_div
=>
100
,
g_1_pulse_energ
=>
100
,
g_max_temp_rise
=>
10000
g_1_pulse_energ
=>
x"2670"
,
--g_max_temp_rise => x"00000F4240" --10^6
g_max_temp_rise
=>
x"02540BE400"
--10^10
)
port
map
(
clk_i
=>
clk_20
,
...
...
@@ -189,10 +194,10 @@ architecture behav of testbench is
--============================================================================
p_clk_20
:
process
begin
clk_20
<=
'0'
;
wait
for
c_clk_20_per
/
2
;
clk_20
<=
'1'
;
wait
for
c_clk_20_per
/
2
;
clk_20
<=
'0'
;
wait
for
c_clk_20_per
/
2
;
end
process
p_clk_20
;
--============================================================================
-- Random number generator
...
...
@@ -234,10 +239,13 @@ end process p_ran_gen;
-- Pulse stimuli
--============================================================================
p_stim_burst
:
process
p_stim_burst
1
:
process
variable
interval
:
time
;
-- := 1000 ns;
begin
--while t_sim1 < 5000000 ns loop
while
true
loop
t_sim1
<=
NOW
-
t_start
;
if
random_intervals
then
interval
:
=
rand_num
*
1
ns
;
else
...
...
@@ -250,7 +258,21 @@ end process p_ran_gen;
burst_train
<=
'0'
;
end
loop
;
end
process
p_stim_burst
;
-- while t_sim2 < 2000000 ns loop
-- t_sim2 <= NOW - t_sim1;
-- if random_intervals then
-- interval := rand_num * 1 ns;
-- else
-- interval := 5000 ns;
-- end if;
-- burst_train <= '0';
-- wait for interval;
-- burst_train <= '1';
-- wait for 250 ns;
-- burst_train <= '0';
-- end loop;
end
process
p_stim_burst1
;
-- p_write_output : process (temp_rise_counter)
...
...
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