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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
fc3445d6
Commit
fc3445d6
authored
Jan 22, 2018
by
Denia Bouhired-Ferrag
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Adds the words golden and release to golden and release files respectively
parent
683170d5
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3 changed files
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73 additions
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65 deletions
+73
-65
conv_ttl_blo.xise
syn/Golden/conv_ttl_blo.xise
+43
-23
conv_ttl_blo.vhd
top/Golden/conv_ttl_blo.vhd
+10
-15
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+20
-27
No files found.
syn/Golden/conv_ttl_blo.xise
View file @
fc3445d6
...
...
@@ -25,28 +25,28 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
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"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
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/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/modules/conv_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
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xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
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/>
</file>
<file
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xil_pn:type=
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>
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<association
xil_pn:name=
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</file>
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xil_pn:type=
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xil_pn:seqID=
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<association
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xil_pn:seqID=
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<file
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xil_pn:type=
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<association
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xil_pn:type=
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>
<association
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...
...
@@ -79,7 +79,7 @@
<association
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"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
29
"
/>
<association
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xil_pn:seqID=
"
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<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -94,7 +94,7 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
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/>
<association
xil_pn:name=
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xil_pn:seqID=
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9
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<file
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"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
...
...
@@ -109,10 +109,10 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
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<association
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xil_pn:seqID=
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<association
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xil_pn:seqID=
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...
...
@@ -127,10 +127,10 @@
<association
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"Implementation"
xil_pn:seqID=
"8"
/>
</file>
<file
xil_pn:name=
"../../top/Golden/conv_ttl_blo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
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xil_pn:seqID=
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<association
xil_pn:name=
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/>
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<file
xil_pn:name=
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xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
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<association
xil_pn:name=
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xil_pn:seqID=
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<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
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/>
...
...
@@ -148,7 +148,7 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
7
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<association
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xil_pn:seqID=
"1
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/>
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<file
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xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -250,13 +250,13 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
5
"
/>
<association
xil_pn:name=
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xil_pn:seqID=
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<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
4
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/>
<association
xil_pn:name=
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xil_pn:seqID=
"1
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/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
28
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
31
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/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -346,7 +346,7 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
27
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
30
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -376,16 +376,36 @@
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
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<association
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</file>
<file
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xil_pn:type=
"FILE_VHDL"
>
<association
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"Implementation"
xil_pn:seqID=
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<association
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<file
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"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
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>
<association
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"Implementation"
xil_pn:seqID=
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<association
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/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
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/>
<association
xil_pn:name=
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/>
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<file
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xil_pn:type=
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"BehavioralSimulation"
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xil_pn:type=
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>
<association
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<association
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xil_pn:seqID=
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<association
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<file
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<association
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xil_pn:seqID=
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<association
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...
...
@@ -544,7 +564,7 @@
<property
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xil_pn:value=
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xil_pn:valueState=
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<property
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xil_pn:valueState=
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<property
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xil_pn:value=
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xil_pn:valueState=
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/>
<property
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"MultiBoot: Starting Address for Golden Configuration spartan6"
xil_pn:value=
"0x0
0000000"
xil_pn:valueState=
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default"
/>
<property
xil_pn:name=
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xil_pn:value=
"0x0
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xil_pn:valueState=
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default"
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<property
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xil_pn:value=
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xil_pn:value=
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<property
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xil_pn:value=
"0x0000"
xil_pn:valueState=
"default"
/>
...
...
top/Golden/conv_ttl_blo.vhd
View file @
fc3445d6
...
...
@@ -5,7 +5,8 @@
--==============================================================================
--
-- description:
-- description: GOLDEN FIRMWARE
--
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
-- components needed in the design and generates the necessary logic for
-- pulse conversion to occur on each channel.
...
...
@@ -222,8 +223,6 @@ architecture arch of conv_ttl_blo is
signal
led_rear
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
-- I2C LEDs
signal
led_i2c
:
std_logic
;
-- System error LED
...
...
@@ -321,21 +320,19 @@ begin
-- Switch inputs for reflection in status register
sw_gp
<=
not
sw_gp_n_i
;
-- Burst mode functionality is enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n
<=
'0'
when
pcbrev_i
(
5
downto
0
)
>=
"010000"
else
'1'
;
--*******************************************************************************
--*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--*******************************************************************************
--*******************************************************************************
--*******************************************************************************
--*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--*******************************************************************************
--*******************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
...
...
@@ -343,8 +340,6 @@ begin
cmp_conv_common
:
conv_common_gw
generic
map
(
g_nr_chans
=>
6
,
g_nr_inv_chans
=>
4
,
g_board_id
=>
c_board_id
,
...
...
top/Release/conv_ttl_blo.vhd
View file @
fc3445d6
...
...
@@ -3,9 +3,8 @@
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--==============================================================================
-- description: RELEASE FIRMWARE
--
-- description:
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
-- components needed in the design and generates the necessary logic for
-- pulse conversion to occur on each channel.
...
...
@@ -222,8 +221,6 @@ architecture arch of conv_ttl_blo is
signal
led_rear
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
-- I2C LEDs
signal
led_i2c
:
std_logic
;
-- System error LED
...
...
@@ -252,7 +249,8 @@ begin
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
-- unnecessary power consumption by the counter
p_ttlbar_nosig
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
...
...
@@ -315,27 +313,24 @@ begin
-- Line inputs for reflection in status register
line_ttl
<=
not
ttl_n_i
;
line_invttl
<=
not
inv_n_i
;
line_blo
<=
blo_i
;
-- Switch inputs for reflection in status register
sw_gp
<=
not
sw_gp_n_i
;
-- Burst mode functionality is enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n
<=
'0'
when
pcbrev_i
(
5
downto
0
)
>=
"010000"
else
'1'
;
--*******************************************************************************
--*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--*******************************************************************************
--*******************************************************************************
--*******************************************************************************
--*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--*******************************************************************************
--*******************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
...
...
@@ -343,8 +338,6 @@ begin
cmp_conv_common
:
conv_common_gw
generic
map
(
g_nr_chans
=>
6
,
g_nr_inv_chans
=>
4
,
g_board_id
=>
c_board_id
,
...
...
@@ -353,9 +346,9 @@ begin
g_pgen_pwidth_lg
=>
24
,
g_pgen_pwidth_sh
=>
5
,
g_pgen_pperiod_cont
=>
4800
,
-- M
in
imum period supported for 1.2us pulse ~ max freq 104kHz
-- M
ax
imum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg
=>
191
,
-- M
in
imum period supported for 250ns pulse ~ max freq 2MHz
-- M
ax
imum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh
=>
9
,
g_pgen_gf_len
=>
1
,
g_temp_decre_step_lg
=>
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
2500
,
731
,
220
,
250
,
40
,
85
,
50
,
125
),
...
...
@@ -388,14 +381,14 @@ begin
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i
=>
burst_en_n
,
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
pulse_width_sel_n_i
=>
sw_gp_n_i
(
1
),
-- Channel enable
global_ch_oen_o
=>
global_oen_o
,
pulse_front_oen_o
=>
ttl_oen_o
,
...
...
@@ -418,7 +411,7 @@ begin
-- inverted channel leds
led_inv_pulse_o
=>
led_inv_pulse
,
-- I2C LED signals -- conect to a bicolor LED of choice
-- I2C LED signals -- con
n
ect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o
=>
led_i2c
,
...
...
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