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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
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f943e5f2
Commit
f943e5f2
authored
Feb 03, 2014
by
Theodor-Adrian Stana
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doc: Updated no-sig-detect block figure and fixed small errors in memory map
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
5dcc4b58
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no-sig-detect.svg
doc/hdlguide/fig/no-sig-detect.svg
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hdlguide-conv-ttl-blo.bib
doc/hdlguide/hdlguide-conv-ttl-blo.bib
+1
-1
hdlguide-conv-ttl-blo.tex
doc/hdlguide/hdlguide-conv-ttl-blo.tex
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doc/hdlguide/fig/no-sig-detect.svg
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doc/hdlguide/hdlguide-conv-ttl-blo.bib
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f943e5f2
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howpublished = {\url{www.ohwr.org/attachments/download/2324/ELMA_SNMP_specification.pdf}}
}
@misc{rtm-det
ect
,
@misc{rtm-det,
title = {{Rear Transition Module detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
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f943e5f2
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...
@@ -554,7 +554,7 @@ input in order to generate a pulse at the output, logic external to the block
caters for the different types of signals that arrive on CONV-TTL-BLO inputs.
Most of this external logic is on the TTL pulse side, where both TTL and TTL-BAR
pulses may arrive. As described in Section 4.3 of the CONV-TTL-BLO User Guide
\cite
{
ctb-ug
}
,
pulses may arrive. As described in Section 4.3 of the CONV-TTL-BLO User Guide
~
\cite
{
ctb-ug
}
,
if a wire is not plugged in when TTL-BAR pulses are input, a continuous logic high level
on the line would inhibit pulses arriving on the blocking side from triggering a pulse
generation. This is why the
\textit
{
no signal detect
}
block has been implemented.
...
...
@@ -976,7 +976,7 @@ $reg. index = \frac{addr}{4} + 1$
\begin{tabular}
{
l l c c p
{
.35
\textwidth
}}
\textbf
{
Bits
}
&
\textbf
{
Field
}
&
\textbf
{
Access
}
&
\textbf
{
Default
}
&
\textbf
{
Description
}
\\
7..0
&
GWVERS
&
R/O
&
X
&
g
ateware version
\\
7..0
&
GWVERS
&
R/O
&
X
&
G
ateware version
\\
15..8
&
SWITCHES
&
R/O
&
X
&
Switch status
\\
21..16
&
RTM
&
R/O
&
X
&
RTM detection lines
\\
22
&
CWDTO
&
R/W
&
0
&
Communication watchdog timeout
\\
...
...
@@ -1022,7 +1022,7 @@ $reg. index = \frac{addr}{4} + 1$
\textbf
{
Bits
}
&
\textbf
{
Field
}
&
\textbf
{
Access
}
&
\textbf
{
Default
}
&
\textbf
{
Description
}
\\
0
&
RST
\_
UNLOCK
&
R/W
&
0
&
Reset bit unlock
\\
1
&
RST
&
R/W
&
0
&
Reset bit
\\
9..2
&
MPT
&
W/O
&
0
&
Manual Pulse Trigger
control
\\
9..2
&
MPT
&
W/O
&
0
&
Manual Pulse Trigger
\\
31..10
&
\textit
{
Reserved
}
&
--
&
X
&
\\
\end{tabular}
...
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