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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
f7b0232e
Commit
f7b0232e
authored
Jan 28, 2014
by
Theodor-Adrian Stana
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hdl: Added input pulse counters
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
bffe180c
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4 changed files
with
325 additions
and
65 deletions
+325
-65
conv_regs.vhd
modules/Release/conv_regs.vhd
+104
-8
conv_regs.wb
modules/Release/conv_regs.wb
+101
-0
conv_ttl_blo.ucf
top/Release/conv_ttl_blo.ucf
+1
-0
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+119
-57
No files found.
modules/Release/conv_regs.vhd
View file @
f7b0232e
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created :
Fri Dec 6 15:43:55 2013
-- Created :
Mon Jan 27 15:46:19 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
...
...
@@ -18,7 +18,7 @@ entity conv_regs is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_adr_i
:
in
std_logic_vector
(
3
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
...
...
@@ -46,7 +46,31 @@ entity conv_regs is
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o
:
out
std_logic
;
reg_cr_rst_i
:
in
std_logic
;
reg_cr_rst_load_o
:
out
std_logic
reg_cr_rst_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 Pulse Counter Register'
reg_ch1pcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch1pcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch1pcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 Pulse Counter Register'
reg_ch2pcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch2pcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch2pcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 Pulse Counter Register'
reg_ch3pcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch3pcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch3pcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 Pulse Counter Register'
reg_ch4pcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch4pcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch4pcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 Pulse Counter Register'
reg_ch5pcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch5pcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch5pcr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 Pulse Counter Register'
reg_ch6pcr_o
:
out
std_logic_vector
(
31
downto
0
);
reg_ch6pcr_i
:
in
std_logic_vector
(
31
downto
0
);
reg_ch6pcr_load_o
:
out
std_logic
);
end
conv_regs
;
...
...
@@ -56,7 +80,7 @@ signal ack_sreg : std_logic_vector(9 downto 0);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
3
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
...
...
@@ -82,6 +106,12 @@ begin
reg_sr_i2c_wdto_load_o
<=
'0'
;
reg_cr_rst_unlock_load_o
<=
'0'
;
reg_cr_rst_load_o
<=
'0'
;
reg_ch1pcr_load_o
<=
'0'
;
reg_ch2pcr_load_o
<=
'0'
;
reg_ch3pcr_load_o
<=
'0'
;
reg_ch4pcr_load_o
<=
'0'
;
reg_ch5pcr_load_o
<=
'0'
;
reg_ch6pcr_load_o
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -91,22 +121,34 @@ begin
reg_sr_i2c_wdto_load_o
<=
'0'
;
reg_cr_rst_unlock_load_o
<=
'0'
;
reg_cr_rst_load_o
<=
'0'
;
reg_ch1pcr_load_o
<=
'0'
;
reg_ch2pcr_load_o
<=
'0'
;
reg_ch3pcr_load_o
<=
'0'
;
reg_ch4pcr_load_o
<=
'0'
;
reg_ch5pcr_load_o
<=
'0'
;
reg_ch6pcr_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
reg_sr_i2c_wdto_load_o
<=
'0'
;
reg_cr_rst_unlock_load_o
<=
'0'
;
reg_cr_rst_load_o
<=
'0'
;
reg_ch1pcr_load_o
<=
'0'
;
reg_ch2pcr_load_o
<=
'0'
;
reg_ch3pcr_load_o
<=
'0'
;
reg_ch4pcr_load_o
<=
'0'
;
reg_ch5pcr_load_o
<=
'0'
;
reg_ch6pcr_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
case
rwaddr_reg
(
3
downto
0
)
is
when
"00
00
"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_id_bits_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
when
"0
00
1"
=>
if
(
wb_we_i
=
'1'
)
then
reg_sr_i2c_wdto_load_o
<=
'1'
;
end
if
;
...
...
@@ -125,7 +167,7 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
when
"
00
10"
=>
if
(
wb_we_i
=
'1'
)
then
reg_cr_rst_unlock_load_o
<=
'1'
;
reg_cr_rst_load_o
<=
'1'
;
...
...
@@ -164,6 +206,48 @@ begin
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0011"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch1pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch1pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0100"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch2pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch2pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0101"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch3pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch3pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0110"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch4pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch4pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0111"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch5pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch5pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
if
(
wb_we_i
=
'1'
)
then
reg_ch6pcr_load_o
<=
'1'
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
reg_ch6pcr_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
...
...
@@ -187,6 +271,18 @@ begin
reg_cr_rst_unlock_o
<=
wrdata_reg
(
0
);
-- Reset bit
reg_cr_rst_o
<=
wrdata_reg
(
1
);
-- bits
reg_ch1pcr_o
<=
wrdata_reg
(
31
downto
0
);
-- bits
reg_ch2pcr_o
<=
wrdata_reg
(
31
downto
0
);
-- bits
reg_ch3pcr_o
<=
wrdata_reg
(
31
downto
0
);
-- bits
reg_ch4pcr_o
<=
wrdata_reg
(
31
downto
0
);
-- bits
reg_ch5pcr_o
<=
wrdata_reg
(
31
downto
0
);
-- bits
reg_ch6pcr_o
<=
wrdata_reg
(
31
downto
0
);
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
modules/Release/conv_regs.wb
View file @
f7b0232e
...
...
@@ -3,6 +3,8 @@ peripheral {
hdl_entity = "conv_regs";
prefix = "reg";
-- Board ID register
reg {
name = "Board ID Register";
description = "Bits of ID register, defaulting to ASCII string TBLO";
...
...
@@ -17,6 +19,8 @@ peripheral {
};
};
-- Status register
reg {
name = "Status Register";
description = "Contains various board status information";
...
...
@@ -55,6 +59,9 @@ peripheral {
load = LOAD_EXT;
};
};
-- Control Register
reg {
name = "Control Register";
description = "Contains bits that control operation of the converter modules";
...
...
@@ -101,6 +108,8 @@ peripheral {
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- Logic reset bits
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
...
...
@@ -122,4 +131,96 @@ peripheral {
load = LOAD_EXT;
};
};
-- Pulse counter registers, R/W access from SysMon
reg {
name = "CH1 Pulse Counter Register";
prefix = "ch1pcr";
description = "Read/write register providing the values of the pulse counter\
on CH1";
field {
name = "bits";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH2 Pulse Counter Register";
prefix = "ch2pcr";
description = "Read/write register providing the values of the pulse counter\
on CH2";
field {
name = "bits";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH3 Pulse Counter Register";
prefix = "ch3pcr";
description = "Read/write register providing the values of the pulse counter\
on CH3";
field {
name = "bits";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH4 Pulse Counter Register";
prefix = "ch4pcr";
description = "Read/write register providing the values of the pulse counter\
on CH4";
field {
name = "bits";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH5 Pulse Counter Register";
prefix = "ch5pcr";
description = "Read/write register providing the values of the pulse counter\
on CH5";
field {
name = "bits";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH6 Pulse Counter Register";
prefix = "ch6pcr";
description = "Read/write register providing the values of the pulse counter\
on CH6";
field {
name = "bits";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
top/Release/conv_ttl_blo.ucf
View file @
f7b0232e
...
...
@@ -453,3 +453,4 @@ NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
top/Release/conv_ttl_blo.vhd
View file @
f7b0232e
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