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C
Conv TTL Blocking - Gateware
Commit f6ae6361 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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changed link coloring in pdfs

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doc/hdlguide/fig/bicolor-led.svg
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doc/hdlguide/fig/no-sig-detect.svg
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
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......@@ -2,12 +2,21 @@
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
% Color package
\usepackage[usenames,dvipsnames]{color}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{color}
\usepackage[toc,page]{appendix}
% Header and footer customization
......@@ -536,7 +545,7 @@ See Appendix~\ref{app:memmap-csr} for more information.
\label{sec:periphs-multiboot}
The MultiBoot module offers the remote reprogramming capabilities for the
CONV-TTL-BLO board. It offers a set of registers for controlling data writing
CONV-TTL-BLO board. It offers a set of registers for controlling writing a bitstream
to the M25P32 flash chip and for issuing the remote reprogramming command.
For information on the module, refer to its documentation under the
......@@ -708,8 +717,8 @@ following sections list the memory map of each peripheral.
\multicolumn{1}{c}{\textbf{Periph.}} & \multicolumn{2}{c}{\textbf{Address}} & \multicolumn{1}{c}{\textbf{Description}} \\
& \multicolumn{1}{c}{\textbf{Base}} & \multicolumn{1}{c}{\textbf{End}} & \\
\hline
CSR & 0x000 & 0x04 & Control and status register \\
MultiBoot & 0x040 & 0x50 & MultiBoot module \\
CSR & 0x000 & 0x0f & Control and status register \\
MultiBoot & 0x040 & 0x5f & MultiBoot module \\
\hline
\end{tabular}
}
......@@ -724,21 +733,21 @@ following sections list the memory map of each peripheral.
\indent Base address: 0x000
\begin{table}[h]
\begin{tabular}{l c p{.6\textwidth}}
\textbf{Offset} & \textbf{ELMA reg} & \textbf{Description} \\
0x0 & 1 & Board ID register \\
0x4 & 2 & Status register \\
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x0 & BID & Board ID register \\
0x4 & SR & Status register \\
0x8 & \textit{Reserved} & Read undefined; write as 0 \\
0xc & \textit{Reserved} & Read undefined; write as 0 \\
\end{tabular}
\end{table}
\noindent Reserved addresses read undefined and should be written as 0x00000000.
%------------------------------------------------------------------------------
\subsubsection{Board ID register}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..0 & \textit{id} & R/O & 0x424c4f32 & Board ID \\
31..0 & ID & R/O & 0x424c4f32 & Board ID \\
\end{tabular}
\vspace*{11pt}
......@@ -747,7 +756,7 @@ following sections list the memory map of each peripheral.
{
\begin{tabular}{l l}
\textbf{Field} & \textbf{Description} \\
\textit{id} & Board ID (ASCII string \textbf{BLO2}) \\
ID & Board ID (ASCII string \textbf{BLO2}) \\
\end{tabular}
}
......@@ -756,10 +765,10 @@ following sections list the memory map of each peripheral.
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
15..0 & \textit{fwvers} & R/O & X & Firmware version \\
23..16 & \textit{switches} & R/O & X & Switch status \\
29..24 & \textit{rtm} & R/O & X & RTM detection lines \\
31..30 & \textit{reserved} & R/O & X & \\
15..0 & FWVERS & R/O & X & Firmware version \\
23..16 & SWITCHES & R/O & X & Switch status \\
29..24 & RTM & R/O & X & RTM detection lines \\
31..30 & \textit{Reserved} & R/O & X & \\
\end{tabular}
\noindent
......@@ -767,7 +776,7 @@ following sections list the memory map of each peripheral.
\begin{tabular}{l p{.8\textwidth}}
\textbf{Field} & \textbf{Description} \\
\textit{fwvers} & Firmware version \newline
FWVERS & Firmware version \newline
-- leftmost byte \textit{hex value} is major release \textit{decimal value} \newline
-- rightmost byte \textit{hex value} is minor release \textit{decimal value} \newline
e.g. \newline
......@@ -775,17 +784,17 @@ following sections list the memory map of each peripheral.
0x0107 -- v1.07 \newline
0x0274 -- v2.74 \newline
etc. \\
\textit{switches} & Current switch status \newline
SWITCHES & Current switch status \newline
bit 0 -- SW1.1 \newline
bit 1 -- SW1.2 \newline
... \newline
bit 7 -- SW2.4 \newline
\textbf{1} -- switch is \textbf{OFF} \newline
\textbf{0} -- switch is \textbf{ON} \\
\textit{rtm} & RTM detection lines status \newline
RTM & RTM detection lines status \newline
\textbf{0} -- line active \newline
\textbf{1} -- line inactive \\
\textit{reserved} & Write as '0'; read undefined \\
\textit{Reserved} & Write as '0'; read undefined \\
\end{tabular}
}
......@@ -801,13 +810,16 @@ following sections list the memory map of each peripheral.
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x00 & CR & Control Register \\
0x04 & SR & Status register \\
0x08 & GBBAR & Golden Bitstream Base Address Register \\
0x0c & MBBAR & Multiboot Bitstream Base Address Register \\
0x10 & FAR & Flash access register \\
0x14 & \textit{Reserved} & Read undefined; write as 0 \\
0x18 & \textit{Reserved} & Read undefined; write as 0 \\
0x1c & \textit{Reserved} & Read undefined; write as 0 \\
\end{tabular}
}
......
doc/i2c_slave/i2c_slave.tex
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......@@ -2,14 +2,22 @@
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
% Color package
\usepackage[usenames,dvipsnames]{color}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{color}
\usepackage{longtable}
% Header and footer customization
......@@ -42,6 +50,7 @@
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
26-06-2013 & 0.01 & First draft \\
28-10-2013 & 0.02 & Changed PDF link colors \\
\hline
\end{tabular}
}
......
doc/multiboot/multiboot.tex
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......@@ -2,7 +2,18 @@
% Document Header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
% Color package
\usepackage[usenames,dvipsnames]{color}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
......@@ -448,8 +459,7 @@ Up to three data bytes can be sent via the FAR during one transfer phase. These
bytes are written in the DATA fields in little-endian order. The NBYTES field selects
how many of the DATA fields contain bytes to send. Setting XFER to '1' with CS set to
'1' starts the transfer. Setting XFER to '1' with CS set to '0' starts a dummy
transfer, with the flash chip not selected. This can be useful in wait intervals
between flash commands.
transfer, with the flash chip not selected.
The transfer is performed via the \textit{spi\_master} module, which handles the
shifting of each DATA byte to the flash. However, the \textit{spi\_master} module
......@@ -469,7 +479,7 @@ interface than SPI is used to access the FAR register (e.g., the VBCP interface
the CONV-TTL-BLO project~\cite{ctb-proj}). If the interface used to access the FAR
is fast, only one byte in the FAR register may be used, and NBYTES left to 0.
\pagebreak
Appendix~\ref{app:multiple-spi} gives an example of how data can be written to flash.
The following settings are used for the SPI communication (Figure~\ref{fig:spi-mode}).
\begin{itemize}
......@@ -684,9 +694,11 @@ on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
The memory map of the Xilinx MultiBoot module is shown below. The following
sections detail the fields of each register.
\vspace*{11pt}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x00 & CR & Control Register \\
0x04 & SR & Status register \\
......
doc/vbcp_wb/vbcp_wb.pdf
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doc/vbcp_wb/vbcp_wb.tex
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......@@ -2,11 +2,21 @@
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
% Color package
\usepackage[usenames,dvipsnames]{color}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{color}
\usepackage[toc,page]{appendix}
......@@ -44,6 +54,7 @@
14-08-2013 & 0.02 & Second draft \\
22-10-2013 & 0.03 & Added \textit{Access commands} section, updated document according to
changes in protocol \\
29-10-2013 & 0.04 & Changed PDF link colors \\
\hline
\end{tabular}
}
......
hdl/release/syn/conv_ttl_blo.gise
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......@@ -137,6 +137,8 @@
<transform xil_pn:end_ts="1382974529" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3650938198851982977" xil_pn:start_ts="1382974475">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_map.map"/>
......
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