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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
f5603f72
Commit
f5603f72
authored
Jan 25, 2017
by
Denia Bouhired-Ferrag
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Plain Diff
Added support in the top file for PCB version-valid for v4 onwards. Testbench upfdated accordingly
parent
89edb373
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2 changed files
with
46 additions
and
46 deletions
+46
-46
testbenchv4.vhd
sim/Release/testbenchv4.vhd
+21
-8
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+25
-38
No files found.
sim/Release/testbenchv4.vhd
View file @
f5603f72
...
@@ -35,6 +35,7 @@
...
@@ -35,6 +35,7 @@
-- 2016-08-01 Denia Bouhired Based on original testbench.vhd by T. Stana
-- 2016-08-01 Denia Bouhired Based on original testbench.vhd by T. Stana
-- Modified to test all pulse channels and LEDs
-- Modified to test all pulse channels and LEDs
-- In addition to the new inv-ttl LEDs
-- In addition to the new inv-ttl LEDs
-- 2016-01-25 Denia Bouhired Add PCB version input to FPGA
--==============================================================================
--==============================================================================
-- TODO: -
-- TODO: -
--==============================================================================
--==============================================================================
...
@@ -123,6 +124,9 @@ architecture behav of testbench is
...
@@ -123,6 +124,9 @@ architecture behav of testbench is
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
vme_gap_i
:
in
std_logic
;
-- PCB version recognition
pcbrev_i
:
in
std_logic_vector
(
3
downto
0
);
-- Channel enable
-- Channel enable
global_oen_o
:
out
std_logic
;
global_oen_o
:
out
std_logic
;
ttl_oen_o
:
out
std_logic
;
ttl_oen_o
:
out
std_logic
;
...
@@ -272,9 +276,10 @@ architecture behav of testbench is
...
@@ -272,9 +276,10 @@ architecture behav of testbench is
signal
blo_inp
,
blo_outp
:
std_logic_vector
(
6
downto
1
);
signal
blo_inp
,
blo_outp
:
std_logic_vector
(
6
downto
1
);
signal
blo_pulse
:
std_logic_vector
(
6
downto
1
);
signal
blo_pulse
:
std_logic_vector
(
6
downto
1
);
signal
oe
,
blo_oe
,
ttl_oe
,
inv_oe
:
std_logic
;
signal
oe
,
blo_oe
,
ttl_oe
,
inv_oe
:
std_logic
;
--signal ttl_switch_n : std_logic;
signal
switches_n
:
std_logic_vector
(
7
downto
0
);
signal
switches_n
:
std_logic_vector
(
7
downto
0
);
signal
pcbversn
:
std_logic_vector
(
3
downto
0
);
-- I2C signals
-- I2C signals
signal
state_i2c_mst
:
t_state_i2c_mst
;
signal
state_i2c_mst
:
t_state_i2c_mst
;
...
@@ -374,10 +379,12 @@ begin
...
@@ -374,10 +379,12 @@ begin
sda_en_o
=>
sda_en_slv
,
sda_en_o
=>
sda_en_slv
,
-- VME interface
-- VME interface
vme_sysreset_n_i
=>
'1'
,
vme_sysreset_n_i
=>
'1'
,
vme_ga_i
=>
"11110"
,
vme_ga_i
=>
"11110"
,
vme_gap_i
=>
'0'
,
vme_gap_i
=>
'0'
,
pcbrev_i
=>
x"0"
,
-- Output enable lines
-- Output enable lines
global_oen_o
=>
oe
,
global_oen_o
=>
oe
,
ttl_oen_o
=>
ttl_oe
,
ttl_oen_o
=>
ttl_oe
,
...
@@ -399,10 +406,10 @@ begin
...
@@ -399,10 +406,10 @@ begin
led_rear_n_o
=>
pulse_led_rear_n
,
led_rear_n_o
=>
pulse_led_rear_n
,
-- Flash memory lines
-- Flash memory lines
flash_sclk_o
=>
open
,
flash_sclk_o
=>
open
,
flash_cs_n_o
=>
open
,
flash_cs_n_o
=>
open
,
flash_mosi_o
=>
open
,
flash_mosi_o
=>
open
,
flash_miso_i
=>
'Z'
,
flash_miso_i
=>
'Z'
,
-- PLL DACs
-- PLL DACs
-- DAC1: 20 MHz VCXO control
-- DAC1: 20 MHz VCXO control
...
@@ -464,6 +471,12 @@ begin
...
@@ -464,6 +471,12 @@ begin
blo_pulse
<=
blo_outp
when
(
oe
=
'1'
)
and
(
blo_oe
=
'1'
)
else
(
others
=>
'0'
);
blo_pulse
<=
blo_outp
when
(
oe
=
'1'
)
and
(
blo_oe
=
'1'
)
else
(
others
=>
'0'
);
inv_pulse
<=
inv_outp
when
(
oe
=
'1'
)
and
(
inv_oe
=
'1'
)
else
(
others
=>
'0'
);
inv_pulse
<=
inv_outp
when
(
oe
=
'1'
)
and
(
inv_oe
=
'1'
)
else
(
others
=>
'0'
);
--============================================================================
--PCB version
--============================================================================
pcbversn
(
3
downto
0
)
<=
"0100"
;
--For version 4
pcbversn
(
3
downto
0
)
<=
"0011"
;
--For version 3
--============================================================================
--============================================================================
-- Switches
-- Switches
--============================================================================
--============================================================================
...
...
top/Release/conv_ttl_blo.vhd
View file @
f5603f72
...
@@ -82,7 +82,10 @@ entity conv_ttl_blo is
...
@@ -82,7 +82,10 @@ entity conv_ttl_blo is
vme_sysreset_n_i
:
in
std_logic
;
vme_sysreset_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
vme_gap_i
:
in
std_logic
;
-- PCB version recognition
pcbrev_i
:
in
std_logic_vector
(
3
downto
0
);
-- Channel enable
-- Channel enable
global_oen_o
:
out
std_logic
;
global_oen_o
:
out
std_logic
;
ttl_oen_o
:
out
std_logic
;
ttl_oen_o
:
out
std_logic
;
...
@@ -214,9 +217,10 @@ architecture arch of conv_ttl_blo is
...
@@ -214,9 +217,10 @@ architecture arch of conv_ttl_blo is
-- Switch signals (for inverting switch inputs to the common g/w)
-- Switch signals (for inverting switch inputs to the common g/w)
signal
sw_ttl
:
std_logic
;
signal
sw_ttl
:
std_logic
;
signal
sw_burst
:
std_logic
;
signal
burst_en_n
:
std_logic
;
signal
sw_gp
:
std_logic_vector
(
7
downto
0
);
signal
sw_gp
:
std_logic_vector
(
7
downto
0
);
signal
pgen_duty_cycle_div_lg
:
natural
range
8
to
300
;
-- No signal on TTL-BAR
-- No signal on TTL-BAR
signal
ttlbar_nosig_cnt
:
t_ttlbar_nosig_cnt
;
signal
ttlbar_nosig_cnt
:
t_ttlbar_nosig_cnt
;
...
@@ -328,12 +332,16 @@ begin
...
@@ -328,12 +332,16 @@ begin
sw_gp
<=
not
sw_gp_n_i
;
sw_gp
<=
not
sw_gp_n_i
;
-- Switch to determine short or long pulse mode.
-- Switch to determine short or long pulse mode.
--
Short pulses of 250ns will allow for burst mode operation.
--
ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
--
Default or Long pulse mode gives 1.2us pulses and this one will be for constant 4.15kHz frequency operation
--
OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
sw_burst
<=
not
sw_gp_n_i
(
1
);
--short pulses for closed or ON switch
--Note that this burst mode functionality is activated only for PCB ver 4 or later
--The FPGA
burst_en_n
<=
'0'
when
pcbrev_i
>=
"0100"
--Functionality enabled for versions 4 and above
else
'1'
;
--when version is below 4 then disable burst functionality
--============================================================================
--============================================================================
-- Instantiate common generic gateware for converter boards
-- Instantiate common generic gateware for converter boards
...
@@ -350,16 +358,16 @@ begin
...
@@ -350,16 +358,16 @@ begin
g_pgen_fixed_width
=>
true
,
g_pgen_fixed_width
=>
true
,
g_pgen_pwidth_lg
=>
24
,
g_pgen_pwidth_lg
=>
24
,
g_pgen_pwidth_sh
=>
5
,
g_pgen_pwidth_sh
=>
5
,
g_pgen_duty_cycle_div_lg
=>
16
,
--changed from 200
g_pgen_duty_cycle_div_cont
=>
200
,
g_pgen_duty_cycle_div_sh
=>
2
,
g_pgen_duty_cycle_div_lg
=>
8
,
-- Minimum duty cycle supoported for 1.2us pulse ~ max freq 104kHz
g_pgen_duty_cycle_div_sh
=>
2
,
-- Minimum duty cycle supoported for 250ns pulse ~ max freq 2MHz
g_pgen_gf_len
=>
1
,
g_pgen_gf_len
=>
1
,
g_temp_decre_step_lg
=>
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
5750
,
100
,
79
,
13
,
12
,
4
,
5
,
13
),
g_temp_decre_step_lg
=>
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
5750
,
100
,
79
,
13
,
12
,
4
,
5
,
13
),
g_temp_decre_step_sh
=>
(
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
),
g_temp_decre_step_sh
=>
(
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
),
g_burstctrl_1_pulse_temp_rise_lg
=>
x"23040"
,
g_burstctrl_1_pulse_temp_rise_lg
=>
x"23040"
,
g_burstctrl_1_pulse_temp_rise_sh
=>
x"01388"
,
g_burstctrl_1_pulse_temp_rise_sh
=>
x"01388"
,
--g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10
--g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
g_burstctrl_max_temp_lg_sh
=>
x"00000F4240"
,
--10^6 --This value is used to speed up simulation
g_burstctrl_max_temp_lg_sh
=>
x"00000F4240"
,
--10^6
g_with_pulse_cnt
=>
true
,
g_with_pulse_cnt
=>
true
,
g_with_pulse_timetag
=>
true
,
g_with_pulse_timetag
=>
true
,
g_with_man_trig
=>
true
,
g_with_man_trig
=>
true
,
...
@@ -381,8 +389,11 @@ begin
...
@@ -381,8 +389,11 @@ begin
-- Glitch filter active-low enable signal
-- Glitch filter active-low enable signal
gf_en_n_i
=>
sw_gp_n_i
(
0
),
gf_en_n_i
=>
sw_gp_n_i
(
0
),
-- Burst mode or short pulse mode enable signal
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i
=>
sw_gp_n_i
(
1
),
burst_en_n_i
=>
burst_en_n
,
-- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i
=>
sw_gp_n_i
(
1
),
-- Channel enable
-- Channel enable
global_ch_oen_o
=>
global_oen_o
,
global_ch_oen_o
=>
global_oen_o
,
...
@@ -403,11 +414,7 @@ begin
...
@@ -403,11 +414,7 @@ begin
-- inverted channel leds
-- inverted channel leds
led_inv_pulse_o
=>
led_inv_pulse
,
led_inv_pulse_o
=>
led_inv_pulse
,
-- I2C LED signals -- conect to a bicolor LED of choice
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o
=>
led_i2c
,
led_i2c_o
=>
led_i2c
,
...
@@ -420,10 +427,6 @@ begin
...
@@ -420,10 +427,6 @@ begin
sda_o
=>
sda_o
,
sda_o
=>
sda_o
,
sda_en_o
=>
sda_en_o
,
sda_en_o
=>
sda_en_o
,
-- VME interface
-- VME interface
vme_sysreset_n_i
=>
vme_sysreset_n_i
,
vme_sysreset_n_i
=>
vme_sysreset_n_i
,
vme_ga_i
=>
vme_ga_i
,
vme_ga_i
=>
vme_ga_i
,
...
@@ -496,13 +499,6 @@ begin
...
@@ -496,13 +499,6 @@ begin
blo_o
<=
pulse_out
;
blo_o
<=
pulse_out
;
-----------------------------------------
-----------------------------------------
-- LED outputs
-- LED outputs
led_front_n_o
<=
not
led_pulse
;
led_front_n_o
<=
not
led_pulse
;
...
@@ -517,20 +513,11 @@ begin
...
@@ -517,20 +513,11 @@ begin
inv_o
<=
inv_pulse_out
;
inv_o
<=
inv_pulse_out
;
--============================================================================
--============================================================================
-- Manual reset for blocking power supply
-- Manual reset for blocking power supply
--============================================================================
--============================================================================
mr_n_o
<=
rst_20_n
;
mr_n_o
<=
rst_20_n
;
--============================================================================
--============================================================================
-- External logic for bicolor LED control
-- External logic for bicolor LED control
--============================================================================
--============================================================================
...
...
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