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Conv TTL Blocking - Gateware
Commit eb11aa6d authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Testbench modifications for burst control module and overall design testbench

parent d297ef22
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Showing with 162 additions and 79 deletions
sim/Release/burst_ctrl_tb.vhd
View file @ eb11aa6d
...@@ -58,12 +58,62 @@ architecture behav of testbench is ...@@ -58,12 +58,62 @@ architecture behav of testbench is
-- Clock periods -- Clock periods
constant c_clk_20_per : time := 50 ns; constant c_clk_20_per : time := 50 ns;
constant random_intervals : boolean := false; constant random_intervals : boolean := false;
constant c_pgen_pwidth : natural := 5;
constant c_pgen_duty_cycle_div : natural := 2;
component conv_pulse_gen is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 2 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
);
end component conv_pulse_gen;
component conv_dyn_burst_ctrl is component conv_dyn_burst_ctrl is
generic generic
( (
g_pwidth : natural range 2 to 40 := 5; g_pwidth : natural range 2 to 40 := 5;
g_temp_decre_step : t_temp_decre_step := (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0); g_temp_decre_step : t_temp_decre_step := (0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0,0);
g_1_pulse_temp_rise :in unsigned (19 downto 0); g_1_pulse_temp_rise :in unsigned (19 downto 0);
g_max_temp :in unsigned (39 downto 0) g_max_temp :in unsigned (39 downto 0)
); );
...@@ -99,7 +149,9 @@ architecture behav of testbench is ...@@ -99,7 +149,9 @@ architecture behav of testbench is
signal burst_train_r_edge : std_logic; signal burst_train_r_edge : std_logic;
signal burst_train_regulated_dyn : std_logic; signal burst_train_regulated_dyn : std_logic;
signal rand_num : integer := 0; signal rand_num : integer := 0;
signal pulse_outp_err_p :std_logic;
signal burst_outp_err_p :std_logic;
signal pulse_outp :std_logic;
signal t_start : TIME := NOW; signal t_start : TIME := NOW;
signal t_sim1 :TIME := 0 ns; signal t_sim1 :TIME := 0 ns;
...@@ -119,29 +171,53 @@ architecture behav of testbench is ...@@ -119,29 +171,53 @@ architecture behav of testbench is
--============================================================================ --============================================================================
-- Instantiate the DUT: Dynamic -- Instantiate the DUT: Dynamic
--============================================================================ --============================================================================
cmp_pulse_gen_sh : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => true,
g_pwidth => c_pgen_pwidth,
g_duty_cycle_div => c_pgen_duty_cycle_div
)
port map
(
clk_i => clk_20,
rst_n_i => rst,
gf_en_n_i => '1',
en_i => '1',
trig_a_i => burst_train,
pulse_err_p_o => pulse_outp_err_p,
pulse_o => pulse_outp,
pulse_r_edge_p_o => burst_train_r_edge ,
pulse_f_edge_p_o => burst_train_f_edge
);
cmp_dut : conv_dyn_burst_ctrl cmp_dut : conv_dyn_burst_ctrl
generic map generic map
( (
g_pwidth => 5, -- g_pwidth => c_pgen_pwidth, --
-- g_temp_decre_step => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
--g_temp_decre_step => (0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13), g_temp_decre_step => (0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_temp_decre_step => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_1_pulse_temp_rise => x"01388", g_1_pulse_temp_rise => x"01388",
--g_1_pulse_temp_rise => x"23040", -- for 1.2us pulse -- g_1_pulse_temp_rise => x"17700", -- for 1.2us pulse
--g_max_temp => x"00000F4240" --10^6 g_max_temp => x"00000F4240" --10^6
-- g_max_temp => x"02540BE400" --10^10
g_max_temp => x"02540BE400" --10^10
) )
port map( port map(
clk_i => clk_20, clk_i => clk_20,
rst_n_i => rst, rst_n_i => rst,
en_i => en, en_i => en,
pulse_burst_i => burst_train, pulse_burst_i => pulse_outp,
pulse_r_edge_p_i => burst_train_r_edge, pulse_r_edge_p_i => burst_train_r_edge,
pulse_f_edge_p_i => burst_train_f_edge, pulse_f_edge_p_i => burst_train_f_edge,
pulse_burst_o => burst_train_regulated_dyn, pulse_burst_o => burst_train_regulated_dyn,
burst_err_p_o => open burst_err_p_o => burst_outp_err_p
); );
...@@ -196,56 +272,58 @@ end process p_ran_gen; ...@@ -196,56 +272,58 @@ end process p_ran_gen;
-- Pulse stimuli -- Pulse stimuli
--============================================================================ --============================================================================
cmp_sync_input : gc_sync_ffs -- cmp_sync_input : gc_sync_ffs
generic map -- generic map
( -- (
g_sync_edge => "positive" -- g_sync_edge => "positive"
) -- )
port map -- port map
( -- (
clk_i => clk_20, -- clk_i => clk_20,
rst_n_i => rst, -- rst_n_i => rst,
data_i => burst_train, -- data_i => burst_train,
npulse_o => burst_train_f_edge, -- npulse_o => burst_train_f_edge,
ppulse_o => burst_train_r_edge -- ppulse_o => burst_train_r_edge
); -- );
p_stim_burst1 : process p_stim_burst1 : process
variable interval : time;-- := 1000 ns; variable interval : time;-- := 1000 ns;
variable period1 : time := 450 ns;--changes pulse frequency
variable period2 : time := 2000 ns;--changes pulse frequency
variable pwidth : time := 250 ns;
begin begin
while t_sim1 < 5000000 us loop while t_sim1 < 50000 us loop
--while true loop -- while true loop
t_sim1 <= NOW - t_start; t_sim1 <= NOW - t_start;
if random_intervals then if random_intervals then
interval := rand_num * 1 ns; interval := rand_num * 1 ns;
if interval < 250 ns then if interval < 250 ns then
interval := 250 ns; interval := 250 ns;
end if; end if;
else else
interval := 1500 ns;--changes pulse frequency interval := period1 - pwidth;
end if; end if;
burst_train <= '0'; burst_train <= '0';
wait for interval; wait for interval;
burst_train <= '1'; burst_train <= '1';
wait for 250 ns;-- changes pulse width wait for pwidth;-- changes pulse width
burst_train <= '0'; burst_train <= '0';
end loop; end loop;
-- while t_sim2 < 50000 us loop while t_sim2 < 100000 us loop
-- t_sim2 <= NOW - t_sim1; t_sim2 <= NOW - t_sim1;
-- if random_intervals then if random_intervals then
-- interval := rand_num * 1 ns; interval := rand_num * 1 ns;
-- else else
-- interval := 1750 ns; interval := period2 - pwidth;
-- end if; end if;
-- burst_train <= '0'; burst_train <= '0';
-- wait for interval; wait for interval;
-- burst_train <= '1'; burst_train <= '1';
-- wait for 250 ns; wait for pwidth;
-- burst_train <= '0'; burst_train <= '0';
-- end loop; end loop;
end process p_stim_burst1; end process p_stim_burst1;
......
sim/Release/testbenchv4.vhd
View file @ eb11aa6d
...@@ -125,7 +125,7 @@ architecture behav of testbench is ...@@ -125,7 +125,7 @@ architecture behav of testbench is
vme_gap_i : in std_logic; vme_gap_i : in std_logic;
-- PCB version recognition -- PCB version recognition
pcbrev_i : in std_logic_vector(3 downto 0); pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable -- Channel enable
global_oen_o : out std_logic; global_oen_o : out std_logic;
...@@ -278,7 +278,7 @@ architecture behav of testbench is ...@@ -278,7 +278,7 @@ architecture behav of testbench is
signal oe, blo_oe, ttl_oe, inv_oe : std_logic; signal oe, blo_oe, ttl_oe, inv_oe : std_logic;
signal switches_n : std_logic_vector(7 downto 0); signal switches_n : std_logic_vector(7 downto 0);
signal pcbversn : std_logic_vector(3 downto 0); signal pcbversn : std_logic_vector(5 downto 0);
-- I2C signals -- I2C signals
signal state_i2c_mst : t_state_i2c_mst; signal state_i2c_mst : t_state_i2c_mst;
...@@ -475,8 +475,8 @@ begin ...@@ -475,8 +475,8 @@ begin
--PCB version --PCB version
--============================================================================ --============================================================================
pcbversn (3 downto 0) <= "0100"; --For version 4 pcbversn (5 downto 0) <= "010000"; --For version 4
--pcbversn (3 downto 0) <= "0011"; --For version 3 --pcbversn (5 downto 0) <= "001100"; --For version 3
--============================================================================ --============================================================================
-- Switches -- Switches
--============================================================================ --============================================================================
...@@ -484,14 +484,14 @@ begin ...@@ -484,14 +484,14 @@ begin
--ttl_switch_n <= '0'; --ttl_switch_n <= '0';
switches_n(7) <= '0'; switches_n(7) <= '0';
-- GF -- GF
switches_n(0) <= '1'; switches_n(0) <= '1'; --1 is off 0 is on
--burst mode is 0 for short pulses and 1 for long pulses --burst mode is 0 for short pulses and 1 for long pulses
switches_n(1) <= '1'; switches_n(1) <= '0';
-- other -- other
switches_n(6 downto 2) <= (others => '1'); switches_n(6 downto 2) <= (others => '0');--set switched to all 1s for v3 testing
-- end process p_set_sw; -- end process p_set_sw;
...@@ -530,34 +530,39 @@ end process p_ran_gen; ...@@ -530,34 +530,39 @@ end process p_ran_gen;
p_stim_pulse : process p_stim_pulse : process
variable interval : time;
variable interval : time;-- := 1000 ns;
variable period : time := 500 ns;--changes pulse frequency
--variable period2 : time := 20000 ns;--changes pulse frequency
variable pwidth : time := 250 ns;
begin begin
ttl_inp_n(6 downto 1) <= (others => '1'); ttl_inp_n(6 downto 1) <= (others => '1');
inv_inp (4 downto 1) <= (others => '0'); inv_inp (4 downto 1) <= (others => '0');
blo_inp(6 downto 1) <= (others => '0'); blo_inp(6 downto 1) <= (others => '0');
wait until inv_flag_n = true; --wait until inv_flag_n = true;
while (inv_flag_n = true) loop while true loop
--while (inv_flag_n = true) loop
if random_intervals then if random_intervals then
interval := rand_num * 1 ns; interval := rand_num * 1 ns;
if interval < 250 ns then if interval < 250 ns then
interval := 250 ns; interval := 250 ns;
end if; end if;
else else
interval := 250 ns;--changes pulse frequency interval := period - pwidth;--changes pulse frequencyccc
end if; end if;
--Activate for loop if all channels should be tested --Activate for loop if all channels should be testfed
for j in 1 downto 1 loop --change loop counter range to change number of channels to be tested --for j in 2 downto 2 loop --change loop counter range to change number of channels to be tested
ttl_inp_n(j) <= '1'; --testing only channel 1 ttl_inp_n(2) <= '1'; --testing only channel 1
wait for interval; wait for interval;
ttl_inp_n(j) <= '0'; ttl_inp_n(2) <= '0';
wait for 250 ns; wait for pwidth;
ttl_inp_n(j) <= '1'; ttl_inp_n(2) <= '1';
if ttl_outp(j) /= '1' then if ttl_outp(2) /= '1' then
assert false report "ttl_outp not '1'" severity warning; assert false report "ttl_outp not '1'" severity warning;
end if; end if;
if blo_outp(j) /= '1' then if blo_outp(2) /= '1' then
assert false report "blo_outp not '1'" severity warning; assert false report "blo_outp not '1'" severity warning;
end if; end if;
...@@ -566,14 +571,14 @@ end process p_ran_gen; ...@@ -566,14 +571,14 @@ end process p_ran_gen;
--blo_inp(j) <= '1'; --blo_inp(j) <= '1';
--wait for 1 us; --wait for 1 us;
--blo_inp(j) <= '0'; --blo_inp(j) <= '0';
if ttl_outp(j) /= '1' then if ttl_outp(2) /= '1' then
assert false report "ttl_outp not '1'" severity warning; assert false report "ttl_outp not '1'" severity warning;
end if; end if;
--if blo_outp(j) /= '1' then --if blo_outp(j) /= '1' then
-- assert false report "blo_outp not '1'" severity warning; -- assert false report "blo_outp not '1'" severity warning;
--end if; --end if;
end loop; --end loop;
while (inv_flag_n = false) loop while (inv_flag_n = false) loop
...@@ -608,12 +613,12 @@ end loop; ...@@ -608,12 +613,12 @@ end loop;
wait; wait;
end process; end process;
--============================================================================ -- ============================================================================
-- I2C master -- I2C master
--============================================================================ -- ============================================================================
------------------------------------------------------------------------------ --------------------------------------------------------------------------
-- First, the component instantiation -- First, the component instantiation
------------------------------------------------------------------------------ --------------------------------------------------------------------------
cmp_master : i2c_master_byte_ctrl cmp_master : i2c_master_byte_ctrl
port map port map
( (
...@@ -624,7 +629,7 @@ end loop; ...@@ -624,7 +629,7 @@ end loop;
clk_cnt => x"0027", clk_cnt => x"0027",
-- input signals input signals
start => mst_sta, start => mst_sta,
stop => mst_sto, stop => mst_sto,
read => mst_rd, read => mst_rd,
...@@ -632,14 +637,14 @@ end loop; ...@@ -632,14 +637,14 @@ end loop;
ack_in => mst_ack, ack_in => mst_ack,
din => mst_dat_in, din => mst_dat_in,
-- output signals output signals
cmd_ack => mst_cmd_ack, cmd_ack => mst_cmd_ack,
ack_out => ack_fr_slv, ack_out => ack_fr_slv,
i2c_busy => open, i2c_busy => open,
i2c_al => open, i2c_al => open,
dout => mst_dat_out, dout => mst_dat_out,
-- i2c lines i2c lines
scl_i => scl, scl_i => scl,
scl_o => scl_fr_mst, scl_o => scl_fr_mst,
scl_oen => scl_en_mst, scl_oen => scl_en_mst,
...@@ -648,15 +653,15 @@ end loop; ...@@ -648,15 +653,15 @@ end loop;
sda_oen => sda_en_mst sda_oen => sda_en_mst
); );
-- Then, the tri-state_i2c_mst buffers on the line Then, the tri-state_i2c_mst buffers on the line
mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else
'1'; '1';
msda(0) <= sda_fr_mst when (sda_en_mst = '0') else msda(0) <= sda_fr_mst when (sda_en_mst = '0') else
'1'; '1';
------------------------------------------------------------------------------ --------------------------------------------------------------------------
-- Bus model instantiation and connection to master and slaves -- Bus model instantiation and connection to master and slaves
------------------------------------------------------------------------------ --------------------------------------------------------------------------
cmp_i2c_bus : i2c_bus_model cmp_i2c_bus : i2c_bus_model
generic map generic map
( (
...@@ -673,11 +678,11 @@ end loop; ...@@ -673,11 +678,11 @@ end loop;
sda_o => sda sda_o => sda
); );
------------------------------------------------------------------------------ --------------------------------------------------------------------------
-- This FSM controls the signals to the master component to implement the I2C -- This FSM controls the signals to the master component to implement the I2C
-- protocol defined together with ELMA. The FSM is controlled by the -- protocol defined together with ELMA. The FSM is controlled by the
-- stimuli process below -- stimuli process below
------------------------------------------------------------------------------ --------------------------------------------------------------------------
p_mst_fsm : process (clk_20) is p_mst_fsm : process (clk_20) is
begin begin
if rising_edge(clk_20) then if rising_edge(clk_20) then
...@@ -859,9 +864,9 @@ end loop; ...@@ -859,9 +864,9 @@ end loop;
end if; end if;
end process p_mst_fsm; end process p_mst_fsm;
------------------------------------------------------------------------------ --------------------------------------------------------------------------
-- Process to "stimulate" the master FSM above -- Process to "stimulate" the master FSM above
------------------------------------------------------------------------------ --------------------------------------------------------------------------
p_stim_mst_fsm : process (rst_n, inv_flag_n, state_i2c_mst) p_stim_mst_fsm : process (rst_n, inv_flag_n, state_i2c_mst)
begin begin
if (rst_n = '0') then if (rst_n = '0') then
......
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