Commit e7c9200f authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Add glitch filter to gateware, which was previously omitted

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent d46cdc91
...@@ -173,8 +173,8 @@ architecture behav of conv_ttl_blo is ...@@ -173,8 +173,8 @@ architecture behav of conv_ttl_blo is
-- next minor release v1.1 c_fwvers = x"11"; -- next minor release v1.1 c_fwvers = x"11";
-- 13 minor releases later v1.14 c_fwvers = x"1e"; -- 13 minor releases later v1.14 c_fwvers = x"1e";
-- next major release v2.0 c_fwvers = x"20"; -- next major release v2.0 c_fwvers = x"20";
-- - version 0.0 is golden firmware version for MultiBoot fallback -- - version 0.1 is golden firmware version for MultiBoot fallback
constant c_fwvers : std_logic_vector(7 downto 0) := x"00"; constant c_fwvers : std_logic_vector(7 downto 0) := x"01";
-- Number of Wishbone masters and slaves, for wb_crossbar -- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1; constant c_nr_masters : natural := 1;
...@@ -214,6 +214,13 @@ architecture behav of conv_ttl_blo is ...@@ -214,6 +214,13 @@ architecture behav of conv_ttl_blo is
c_slv_multiboot => c_mask_multiboot c_slv_multiboot => c_mask_multiboot
); );
------------------------------------------------------------------------------
-- Pulse generator constants
------------------------------------------------------------------------------
constant c_pulse_gen_pwidth : positive := 24;
constant c_pulse_gen_duty_cycle_div : positive := 200;
constant c_pulse_gen_gf_len : positive := 1;
--============================================================================ --============================================================================
-- Component declarations -- Component declarations
--============================================================================ --============================================================================
...@@ -377,6 +384,8 @@ architecture behav of conv_ttl_blo is ...@@ -377,6 +384,8 @@ architecture behav of conv_ttl_blo is
signal trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1); signal trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge : std_logic_vector(g_nr_ttl_chan downto 1); signal trig_synced_edge : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1); signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_degl : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_chan : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter -- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt; signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
...@@ -659,31 +668,10 @@ begin ...@@ -659,31 +668,10 @@ begin
--============================================================================ --============================================================================
-- Output enable logic -- Output enable logic
--============================================================================ --============================================================================
-- The general output enable is set first and the blocking, TTL fpga_oe_o <= '1';
-- and INV output enable signals are set one clock cycle later. fpga_blo_oe_o <= '1';
p_oe : process(clk20_vcxo_i) fpga_trig_ttl_oe_o <= '1';
begin fpga_inv_oe_o <= '1';
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
--============================================================================ --============================================================================
-- TTL and blocking pulse generation logic -- TTL and blocking pulse generation logic
...@@ -703,17 +691,6 @@ begin ...@@ -703,17 +691,6 @@ begin
-- Generate pulse repetition logic -- Generate pulse repetition logic
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
gen_ttl_pulse_generators : for i in 1 to g_nr_ttl_chan generate gen_ttl_pulse_generators : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk20_vcxo_i domain
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i)
);
-- Process to detect lack of signal on TTL line -- Process to detect lack of signal on TTL line
-- --
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable -- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
...@@ -734,12 +711,55 @@ begin ...@@ -734,12 +711,55 @@ begin
end if; end if;
end process p_ttlbar_nosig; end process p_ttlbar_nosig;
-- First, resync the trigger signal into clk20_vcxo_i domain
--
-- Reset value is '1' to keep to the post-v2.0 releases, where a pulse would
-- be counted by the pulse counter on startup, when the board is in TTL-BAR
-- repetition mode.
--
-- Due to the FPGA logic reset time of 100ms, all inputs should settle by the
-- time the reset is over, so not resetting the glitch filter is safe
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => '1',
data_i => trig_a(i),
synced_o => trig_synced(i)
);
-- Deglitch synchronized trigger signal
--
-- Reset value is '1' to keep to the post-v2.0 releases, where a pulse would
-- be counted by the pulse counter on startup, when the board is in TTL-BAR
-- repetition mode.
--
-- Due to the FPGA logic reset time of 100ms, all inputs should settle by the
-- time the reset is over, so not resetting the glitch filter is safe
cmp_inp_glitch_filt : gc_glitch_filt
generic map
(
g_len => c_pulse_gen_gf_len
)
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => '1',
dat_i => trig_synced(i),
dat_o => trig_degl(i)
);
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan(i) <= trig_a(i) when (extra_switch_n_i(1) = '1') else
trig_degl(i);
-- Output pulse generators -- Output pulse generators
cmp_ttl_pulse_gen : ctblo_pulse_gen cmp_ttl_pulse_gen : ctblo_pulse_gen
generic map generic map
( (
g_pwidth => 24, g_pwidth => c_pulse_gen_pwidth,
g_duty_cycle_div => 200 g_duty_cycle_div => c_pulse_gen_duty_cycle_div
) )
port map port map
( (
...@@ -747,7 +767,7 @@ begin ...@@ -747,7 +767,7 @@ begin
rst_n_i => rst_n, rst_n_i => rst_n,
en_i => '1', en_i => '1',
gf_en_n_i => extra_switch_n_i(1), gf_en_n_i => extra_switch_n_i(1),
trig_a_i => trig_a(i), trig_a_i => trig_chan(i),
pulse_o => pulse_outp(i) pulse_o => pulse_outp(i)
); );
...@@ -789,10 +809,8 @@ begin ...@@ -789,10 +809,8 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Pulse status LED output assignments -- Pulse status LED output assignments
pulse_front_led_n_o <= (not pulse_leds) when (ttl_oe = '1') else pulse_front_led_n_o <= not pulse_leds;
(others => '1'); pulse_rear_led_n_o <= not pulse_leds;
pulse_rear_led_n_o <= (not pulse_leds) when (blo_oe = '1') else
(others => '1');
--============================================================================ --============================================================================
-- General-purpose INV TTL outputs -- General-purpose INV TTL outputs
......
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