Commit e0f2b49a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Fix pulse inhibit issue

parent 655fa773
......@@ -171,6 +171,7 @@ architecture behav of ctblo_pulse_gen is
-- Inhibit first pulse
signal inh_fp_gf_on : std_logic;
signal inh_fp_gf_on_d0 : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
......@@ -252,16 +253,23 @@ begin
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
inh_fp_gf_on <= '1';
inh_fp_gf_on_d0 <= '1';
pulse_err_p_o <= '0';
elsif (en_i = '1') then
-- On the first cycle after the reset, the pulse channel needs to be
-- On the first two cycle after reset, the pulse channel needs to be
-- inhibited when the converter board is in TTL-BAR repetition mode,
-- since in this mode, an unconnected channel is HIGH for the first
-- 100us until the "no signal detect" block triggers, and the HIGH level
-- on the line will get interpreted by the trigger delay (due to its reset
-- state) as a rising edge on the line, thus triggering a pulse.
--
-- This is only needed when the glitch filter is ON, since when it is OFF,
-- as the unconnected channel is HIGH for the first 100us, no rising-edge
-- on the channel exists and the p_pulse_gf_off process above is not
-- triggered.
inh_fp_gf_on_d0 <= inh_fp_gf_on;
if inh_fp_gf_on = '1' then
inh_fp_gf_on <= '0';
inh_fp_gf_on <= '0';
end if;
-- State machine logic
......@@ -281,7 +289,7 @@ begin
state <= GEN_GF_OFF;
end if;
else
if (trig_gf_on_r_edge_p = '1') and (inh_fp_gf_on = '0') then
if (trig_gf_on_r_edge_p = '1') and (inh_fp_gf_on_d0 = '0') then
state <= GEN_GF_ON;
end if;
end if;
......
......@@ -192,7 +192,7 @@ architecture behav of conv_ttl_blo is
-- next minor release v1.1 c_gwvers = x"11";
-- 13 minor releases later v1.14 c_gwvers = x"1e";
-- next major release v2.0 c_gwvers = x"20";
constant c_gwvers : std_logic_vector(7 downto 0) := x"21";
constant c_gwvers : std_logic_vector(7 downto 0) := x"22";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
......@@ -1224,7 +1224,7 @@ begin
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan(i) <= trig_a(i) when extra_switch_n_i(1) = '1' else
trig_chan(i) <= trig_a(i) when (extra_switch_n_i(1) = '1') else
trig_degl(i);
-- Now, sync this channel trigger signal before passing it to the counters
......
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