Commit dbabef0c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

pulsetest: Change signal names in pulse_gen_gp and changed sync FF reset value

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 44e37666
...@@ -94,11 +94,11 @@ architecture behav of pulse_gen_gp is ...@@ -94,11 +94,11 @@ architecture behav of pulse_gen_gp is
--============================================================================ --============================================================================
-- Signal declarations -- Signal declarations
--============================================================================ --============================================================================
signal inp_delay : unsigned(31 downto 0); signal delay_int : unsigned(31 downto 0);
signal inp_pwidth : unsigned(31 downto 0); signal pwidth_int : unsigned(31 downto 0);
signal inp_freq : unsigned(31 downto 0); signal freq_int : unsigned(31 downto 0);
signal freq_cnt : unsigned(31 downto 0); signal pulse_cnt : unsigned(31 downto 0);
signal delay_cnt : unsigned(31 downto 0); signal delay_cnt : unsigned(31 downto 0);
signal delay_en : std_logic; signal delay_en : std_logic;
...@@ -111,9 +111,9 @@ begin ...@@ -111,9 +111,9 @@ begin
--============================================================================ --============================================================================
-- Convert std_logic_vector inputs to unsigned -- Convert std_logic_vector inputs to unsigned
--============================================================================ --============================================================================
inp_delay <= unsigned(delay_i); delay_int <= unsigned(delay_i);
inp_pwidth <= unsigned(pwidth_i); pwidth_int <= unsigned(pwidth_i);
inp_freq <= unsigned(freq_i); freq_int <= unsigned(freq_i);
--============================================================================ --============================================================================
-- Delay logic -- Delay logic
...@@ -125,13 +125,13 @@ begin ...@@ -125,13 +125,13 @@ begin
delay_en <= '1'; delay_en <= '1';
delay_cnt <= (others => '0'); delay_cnt <= (others => '0');
else else
if (inp_delay = (inp_delay'range => '0')) then if (delay_int = (delay_int'range => '0')) then
delay_en <= '0'; delay_en <= '0';
elsif (delay_en = '1') then elsif (delay_en = '1') then
delay_cnt <= delay_cnt + 1; delay_cnt <= delay_cnt + 1;
if (delay_cnt = inp_delay) then if (delay_cnt = delay_int) then
delay_en <= '0'; delay_en <= '0';
delay_cnt <= (others => '0'); delay_cnt <= (others => '0');
end if; end if;
end if; end if;
end if; end if;
...@@ -145,15 +145,15 @@ begin ...@@ -145,15 +145,15 @@ begin
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then if (rst_n_i = '0') or (en_i = '0') then
freq_cnt <= (others => '0'); pulse_cnt <= (others => '0');
pulse_o <= '0'; pulse_o <= '0';
elsif (delay_en = '0') then elsif (delay_en = '0') then
freq_cnt <= freq_cnt + 1; pulse_cnt <= pulse_cnt + 1;
pulse_o <= '0'; pulse_o <= '0';
if (freq_cnt < inp_pwidth) then if (pulse_cnt < pwidth_int) then
pulse_o <= '1'; pulse_o <= '1';
elsif (freq_cnt = inp_freq-1) then elsif (pulse_cnt = freq_int-1) then
freq_cnt <= (others => '0'); pulse_cnt <= (others => '0');
end if; end if;
end if; end if;
end if; end if;
......
...@@ -831,11 +831,14 @@ begin ...@@ -831,11 +831,14 @@ begin
gen_chan_logic : for i in 1 to g_nr_ttl_chan generate gen_chan_logic : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk20_vcxo_i domain -- First, resync the trigger signal into clk20_vcxo_i domain
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_sync_ffs: gc_sync_ffs cmp_sync_ffs: gc_sync_ffs
port map port map
( (
clk_i => clk20_vcxo_i, clk_i => clk20_vcxo_i,
rst_n_i => rst_n, rst_n_i => '1',
data_i => trig_a(i), data_i => trig_a(i),
synced_o => trig_synced(i), synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i) ppulse_o => trig_synced_edge(i)
......
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