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Conv TTL Blocking - Gateware
Commit d6f11be5 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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conv-common-gw @ a381f447
Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
Subproject commit a381f44777f923edd813b0068742ccbcf694ea71
syn/Golden/conv_ttl_blo.xise 0 → 100644
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syn/Release/conv_ttl_blo.xise
View file @ d6f11be5
......@@ -115,7 +115,7 @@
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<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -123,11 +123,11 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -513,7 +513,7 @@
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
......@@ -541,10 +541,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../sim/Release/fastevent_counter_tb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="chipscope_ila.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -649,9 +646,9 @@
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -692,7 +689,7 @@
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -779,10 +776,11 @@
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -821,8 +819,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/conv_burst_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.conv_burst_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -833,7 +831,7 @@
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
......@@ -845,7 +843,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.conv_burst_ctrl" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
top/Golden/Manifest.py 0 → 100644
View file @ d6f11be5
files = [
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../ip_cores/conv-common-gw"
]
}
top/Golden/conv_ttl_blo.ucf 0 → 100644
View file @ d6f11be5
#==============================================================================
# CERN (BE-CO-HT)
# UCF defintions file for CONV-TTL-BLO gateware
#==============================================================================
#
# author: Theodor Stana (t.stana@cern.ch)
#
# date of creation: 2013-04-26
#
# version: 1.0
#
# description:
# This file contains the pin definitions for the CONV-TTL-BLO FPGA.
#
# references:
# [1] CONV-TTL-BLO schematics from latest version of project at:
# https://edms.cern.ch/nav/EDA-02446
#
#==============================================================================
# GNU LESSER GENERAL PUBLIC LICENSE
#==============================================================================
# This source file is free software; you can redistribute it and/or modify it
# under the terms of the GNU Lesser General Public License as published by the
# Free Software Foundation; either version 2.1 of the License, or (at your
# option) any later version. This source is distributed in the hope that it
# will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
# See the GNU Lesser General Public License for more details. You should have
# received a copy of the GNU Lesser General Public License along with this
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#==============================================================================
# last changes:
# 2013-04-26 Theodor Stana t.stana@cern.ch File modified
# 2016-07-25 Denia Bouhired denia.bouhired@cern.ch Added 4 pins connected to inv channel LEDs
# 2016-07-25 Denia Bouhired denia.bouhired@cern.ch aDDED 4 pins for PCB version recognition
#==============================================================================
# TODO: -
#==============================================================================
#=============================================================================
# CLOCKS AND OUTPUT RESET
#=============================================================================
NET "clk_20_i" LOC = E16;
NET "clk_20_i" TNM_NET = "clk_20_i";
TIMESPEC TSCLK20 = PERIOD "clk_20_i" 20 MHz HIGH 50 %;
NET "clk_125_p_i" LOC = H12;
NET "clk_125_n_i" LOC = G11;
NET "clk_125_p_i" TNM_NET = "clk_125";
TIMESPEC TSCLK125 = PERIOD "clk_125" 125 MHz HIGH 50 %;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
#==============================================================================
# FRONT PANEL
#==============================================================================
#-----------------------------------------------------------------------------
# TTL I/O
#-----------------------------------------------------------------------------
NET "ttl_n_i[0]" LOC = T2;
NET "ttl_n_i[0]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[1]" LOC = U3;
NET "ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[2]" LOC = V5;
NET "ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[3]" LOC = W4;
NET "ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[4]" LOC = T6;
NET "ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[5]" LOC = T3;
NET "ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "ttl_o[0]" LOC = C1;
NET "ttl_o[0]" IOSTANDARD = LVCMOS33;
NET "ttl_o[1]" LOC = F2;
NET "ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "ttl_o[2]" LOC = F5;
NET "ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "ttl_o[3]" LOC = H4;
NET "ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "ttl_o[4]" LOC = J4;
NET "ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "ttl_o[5]" LOC = H2;
NET "ttl_o[5]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# INV-TTL I/O
#-----------------------------------------------------------------------------
NET "inv_n_i[0]" LOC = V2;
NET "inv_n_i[0]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[1]" LOC = W3;
NET "inv_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[2]" LOC = Y2;
NET "inv_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[3]" LOC = AA2;
NET "inv_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_o[0]" LOC = J3;
NET "inv_o[0]" IOSTANDARD = LVCMOS33;
NET "inv_o[1]" LOC = L3;
NET "inv_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_o[2]" LOC = M3;
NET "inv_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_o[3]" LOC = P2;
NET "inv_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_front_n_o[0]" LOC = H5;
NET "led_front_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[0]" DRIVE = 4;
NET "led_front_n_o[0]" SLEW = QUIETIO;
NET "led_front_n_o[1]" LOC = J6;
NET "led_front_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[1]" DRIVE = 4;
NET "led_front_n_o[1]" SLEW = QUIETIO;
NET "led_front_n_o[2]" LOC = K6;
NET "led_front_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[2]" DRIVE = 4;
NET "led_front_n_o[2]" SLEW = QUIETIO;
NET "led_front_n_o[3]" LOC = K5;
NET "led_front_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[3]" DRIVE = 4;
NET "led_front_n_o[3]" SLEW = QUIETIO;
NET "led_front_n_o[4]" LOC = M7;
NET "led_front_n_o[4]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[4]" DRIVE = 4;
NET "led_front_n_o[4]" SLEW = QUIETIO;
NET "led_front_n_o[5]" LOC = M6;
NET "led_front_n_o[5]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[5]" DRIVE = 4;
NET "led_front_n_o[5]" SLEW = QUIETIO;
NET "led_front_inv_n_o[0]" LOC = N6;
NET "led_front_inv_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[0]" DRIVE = 4;
NET "led_front_inv_n_o[0]" SLEW = QUIETIO;
NET "led_front_inv_n_o[1]" LOC = N7;
NET "led_front_inv_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[1]" DRIVE = 4;
NET "led_front_inv_n_o[1]" SLEW = QUIETIO;
NET "led_front_inv_n_o[2]" LOC = U4;
NET "led_front_inv_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[2]" DRIVE = 4;
NET "led_front_inv_n_o[2]" SLEW = QUIETIO;
NET "led_front_inv_n_o[3]" LOC = T4;
NET "led_front_inv_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_inv_n_o[3]" DRIVE = 4;
NET "led_front_inv_n_o[3]" SLEW = QUIETIO;
#------------------------------------------------------------------------------
# Status LEDs
#------------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# PCB version pins
#------------------------------------------------------------------------------
NET "pcbrev_i[0]" LOC = A3;
NET "pcbrev_i[0]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[1]" LOC = A4;
NET "pcbrev_i[1]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[2]" LOC = R4;
NET "pcbrev_i[2]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[3]" LOC = P4;
NET "pcbrev_i[3]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[4]" LOC = V3;
NET "pcbrev_i[4]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[5]" LOC = Y3;
NET "pcbrev_i[5]" IOSTANDARD = LVCMOS33;
#=============================================================================
# Rear panel signals
#=============================================================================
#-----------------------------------------------------------------------------
# Blocking I/O
#-----------------------------------------------------------------------------
NET "blo_i[0]" LOC = Y9;
NET "blo_i[0]" IOSTANDARD = LVCMOS33;
NET "blo_i[0]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "blo_i[1]" LOC = AA10;
NET "blo_i[1]" IOSTANDARD = LVCMOS33;
NET "blo_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "blo_i[2]" LOC = W12;
NET "blo_i[2]" IOSTANDARD = LVCMOS33;
NET "blo_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "blo_i[3]" LOC = AA6;
NET "blo_i[3]" IOSTANDARD = LVCMOS33;
NET "blo_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "blo_i[4]" LOC = Y7;
NET "blo_i[4]" IOSTANDARD = LVCMOS33;
NET "blo_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "blo_i[5]" LOC = AA8;
NET "blo_i[5]" IOSTANDARD = LVCMOS33;
NET "blo_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "blo_o[0]" LOC = W9;
NET "blo_o[0]" IOSTANDARD = LVCMOS33;
NET "blo_o[1]" LOC = T10;
NET "blo_o[1]" IOSTANDARD = LVCMOS33;
NET "blo_o[2]" LOC = V7;
NET "blo_o[2]" IOSTANDARD = LVCMOS33;
NET "blo_o[3]" LOC = U9;
NET "blo_o[3]" IOSTANDARD = LVCMOS33;
NET "blo_o[4]" LOC = T8;
NET "blo_o[4]" IOSTANDARD = LVCMOS33;
NET "blo_o[5]" LOC = R9;
NET "blo_o[5]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_rear_n_o[0]" LOC = AB17;
NET "led_rear_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[0]" DRIVE = 4;
NET "led_rear_n_o[0]" SLEW = QUIETIO;
NET "led_rear_n_o[1]" LOC = AB19;
NET "led_rear_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[1]" DRIVE = 4;
NET "led_rear_n_o[1]" SLEW = QUIETIO;
NET "led_rear_n_o[2]" LOC = AA16;
NET "led_rear_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[2]" DRIVE = 4;
NET "led_rear_n_o[2]" SLEW = QUIETIO;
NET "led_rear_n_o[3]" LOC = AA18;
NET "led_rear_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[3]" DRIVE = 4;
NET "led_rear_n_o[3]" SLEW = QUIETIO;
NET "led_rear_n_o[4]" LOC = AB16;
NET "led_rear_n_o[4]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[4]" DRIVE = 4;
NET "led_rear_n_o[4]" SLEW = QUIETIO;
NET "led_rear_n_o[5]" LOC = AB18;
NET "led_rear_n_o[5]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[5]" DRIVE = 4;
NET "led_rear_n_o[5]" SLEW = QUIETIO;
#=============================================================================
# Channel enable signals
#=============================================================================
NET "global_oen_o" LOC = R3;
NET "global_oen_o" IOSTANDARD = LVCMOS33;
NET "global_oen_o" DRIVE = 4;
NET "global_oen_o" SLEW = QUIETIO;
NET "ttl_oen_o" LOC = N3;
NET "ttl_oen_o" IOSTANDARD = LVCMOS33;
NET "ttl_oen_o" DRIVE = 4;
NET "ttl_oen_o" SLEW = QUIETIO;
NET "inv_oen_o" LOC = P6;
NET "inv_oen_o" IOSTANDARD = LVCMOS33;
NET "inv_oen_o" DRIVE = 4;
NET "inv_oen_o" SLEW = QUIETIO;
NET "blo_oen_o" LOC = P5;
NET "blo_oen_o" IOSTANDARD = LVCMOS33;
NET "blo_oen_o" DRIVE = 4;
NET "blo_oen_o" SLEW = QUIETIO;
#=============================================================================
# VME CONNECTOR SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# I2C lines
#-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_en_o" LOC = H18;
NET "scl_en_o" IOSTANDARD = LVCMOS33;
NET "scl_en_o" DRIVE = 4;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
NET "sda_en_o" LOC = J19;
NET "sda_en_o" IOSTANDARD = LVCMOS33;
NET "sda_en_o" SLEW = FAST;
NET "sda_en_o" DRIVE = 4;
#-----------------------------------------------------------------------------
# System reset line
#-----------------------------------------------------------------------------
NET "vme_sysreset_n_i" LOC = L20;
NET "vme_sysreset_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "vme_ga_i[0]" LOC = H20;
NET "vme_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[1]" LOC = J20;
NET "vme_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[2]" LOC = K19;
NET "vme_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[3]" LOC = K20;
NET "vme_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[4]" LOC = L19;
NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "vme_gap_i" LOC = H19;
NET "vme_gap_i" IOSTANDARD = LVCMOS33;
#=============================================================================
# WHITE RABBIT
#=============================================================================
#-----------------------------------------------------------------------------
# DAC control
#-----------------------------------------------------------------------------
NET "dac125_din_o" LOC = AB14;
NET "dac125_din_o" IOSTANDARD = LVCMOS33;
NET "dac125_sclk_o" LOC = AA14;
NET "dac125_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac125_sync_n_o" LOC = AB15;
NET "dac125_sync_n_o" IOSTANDARD = LVCMOS33;
NET "dac20_din_o" LOC = W14;
NET "dac20_din_o" IOSTANDARD = LVCMOS33;
NET "dac20_sclk_o" LOC = Y14;
NET "dac20_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac20_sync_n_o" LOC = W13;
NET "dac20_sync_n_o" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# SFP connection
#-----------------------------------------------------------------------------
NET "sfp_los_i" LOC = G3;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_i" LOC = K8;
NET "sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_o" LOC = C4;
NET "sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b" LOC = G4;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b" LOC = F3;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o" LOC = E4;
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" LOC = D2;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# FPGA MGT lines
#-----------------------------------------------------------------------------
#NET "mgt_clk0_p_i" LOC = A10;
#NET "mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
#=============================================================================
# OTHER SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# One-wire thermometer data signal
#-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# General-purpose switches
#-----------------------------------------------------------------------------
NET "sw_gp_n_i[0]" LOC = F22;
NET "sw_gp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[1]" LOC = G22;
NET "sw_gp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[2]" LOC = H21;
NET "sw_gp_n_i[2]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[3]" LOC = H22;
NET "sw_gp_n_i[3]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[4]" LOC = J22;
NET "sw_gp_n_i[4]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[5]" LOC = K21;
NET "sw_gp_n_i[5]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[6]" LOC = K22;
NET "sw_gp_n_i[6]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[7]" LOC = L22;
NET "sw_gp_n_i[7]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# RTM detection lines
#-----------------------------------------------------------------------------
NET "rtmm_i[0]" LOC = V21;
NET "rtmm_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[1]" LOC = V22;
NET "rtmm_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[2]" LOC = U22;
NET "rtmm_i[2]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[0]" LOC = W22;
NET "rtmp_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[1]" LOC = Y22;
NET "rtmp_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[2]" LOC = Y21;
NET "rtmp_i[2]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Flash memory
#-----------------------------------------------------------------------------
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = LVCMOS33;
NET "flash_cs_n_o" LOC = AA3;
NET "flash_cs_n_o" IOSTANDARD = LVCMOS33;
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = LVCMOS33;
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = LVCMOS33;
##----------------------------------------------------------------------------
## General purpose
##----------------------------------------------------------------------------
# NET "dbg_header_n_o[0]" LOC = F15;
# NET "dbg_header_n_o[0]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[1]" LOC = F16;
# NET "dbg_header_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[2]" LOC = F17;
# NET "dbg_header_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[3]" LOC = F14;
# NET "dbg_header_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[4]" LOC = H14;
# NET "dbg_header_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[5]" LOC = H13;
# NET "dbg_header_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[0]" LOC = A17;
# NET "dbg_header_n_i[0]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[1]" LOC = A18;
# NET "dbg_header_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[2]" LOC = B18;
# NET "dbg_header_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[3]" LOC = A19;
# NET "dbg_header_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[4]" LOC = A20;
# NET "dbg_header_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[5]" LOC = B20;
# NET "dbg_header_n_i[5]" IOSTANDARD = "LVCMOS33";
top/Golden/conv_ttl_blo.vhd 0 → 100644
View file @ d6f11be5
--==============================================================================
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--==============================================================================
--
-- description: GOLDEN FIRMWARE
--
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
-- components needed in the design and generates the necessary logic for
-- pulse conversion to occur on each channel.
--
-- Details about the HDL design can be found by reading the HDL guide of the
-- project in the doc/ folder.
--
-- dependencies:
-- general-cores repository [1]
-- conv-common-gw repository [2]
--
-- references:
-- [1] Platform-independent core collection on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] Converter common gateware
-- https://www.ohwr.org/projects/conv-common-gw/repository
-- [3] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_ttl_blo is
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- Active-low reset for blocking power supply
mr_n_o : out std_logic;
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
inv_oen_o : out std_logic;
blo_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
blo_i : in std_logic_vector(5 downto 0);
blo_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_n_o : out std_logic_vector(5 downto 0);
led_front_inv_n_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_mod_def0_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_mod_def1_b : inout std_logic;
sfp_mod_def2_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
-- Switches
sw_gp_n_i : in std_logic_vector(7 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- Front panel bicolor LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic
);
end entity conv_ttl_blo;
architecture arch of conv_ttl_blo is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of repetition channels
constant c_NR_CHANS : integer := 6;
constant c_nr_inv_chans : integer := 4;
-- Number of bicolor LED lines & columns
constant c_bicolor_led_lines : integer := 2;
constant c_bicolor_led_cols : integer := 6;
-- Board ID - ASCII string "TBLO"
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-- Gateware version
constant c_gwvers : std_logic_vector(7 downto 0) := x"03";
--============================================================================
-- Type declarations
--============================================================================
type t_ttlbar_nosig_cnt is array (c_nr_chans-1 downto 0) of unsigned(10 downto 0);
-- Array of constants for temperature model implemented for long long mode
type t_temp_decre_step_lg is array (0 to 14) of integer;
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signal
signal rst_20_n : std_logic;
-- TTL & RS485 signals
signal rs485_fs : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_in : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_out : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_blo : std_logic_vector(c_nr_chans-1 downto 0);
signal inhibit_first_pulse : std_logic;
signal inhibit_first_pulse_d0 : std_logic;
signal inhibit_cnt : unsigned(10 downto 0);
-- Temperature model constantstemp_decre_step_lg
signal temp_decre_step_lg : t_temp_decre_step;
signal temp_decre_step_sh : t_temp_decre_step;
-- Line signals -- for reflection in line status register of conv_common_gw
signal line_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal line_invttl : std_logic_vector(3 downto 0);
signal line_blo : std_logic_vector(c_nr_chans-1 downto 0);
-- Switch signals (for inverting switch inputs to the common g/w)
signal sw_ttl : std_logic;
signal burst_en_n : std_logic;
signal sw_gp : std_logic_vector(7 downto 0);
signal pgen_duty_cycle_div_lg : natural range 8 to 300;
-- No signal on TTL-BAR
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig : std_logic_vector(c_nr_chans-1 downto 0);
-- Channel LED signals
signal led_pulse : std_logic_vector(c_nr_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal led_rear : std_logic_vector(c_nr_chans-1 downto 0);
-- I2C LEDs
signal led_i2c : std_logic;
-- System error LED
signal led_syserr : std_logic;
-- Bicolor LED signals
signal bicolor_led_state : std_logic_vector(2*c_bicolor_led_cols*c_bicolor_led_lines-1 downto 0);
signal bicolor_led_col : std_logic_vector(c_bicolor_led_cols-1 downto 0);
signal bicolor_led_line : std_logic_vector(c_bicolor_led_lines-1 downto 0);
signal bicolor_led_line_oen : std_logic_vector(c_bicolor_led_lines-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Channel input logic
--============================================================================
-- TTL switch
sw_ttl <= not sw_gp_n_i(7);
-- The "no signal detect" block
--
-- If the signal line is high for 100 us, the ttlbar_nosig lines disable
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
p_ttlbar_nosig : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
for i in 0 to c_nr_chans-1 loop
if (rst_20_n = '0') or (ttl_n_i(i) = '0') then
ttlbar_nosig(i) <= '0';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif (sw_ttl = '0') then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if (ttlbar_nosig_cnt(i) = 1999) then
ttlbar_nosig(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
end if;
end if;
end loop;
end if;
end process p_ttlbar_nosig;
-- TTL and blocking inputs
pulse_ttl <= not ttl_n_i when sw_ttl = '1' else
ttl_n_i and (not ttlbar_nosig);
pulse_blo <= blo_i;
-- This process has the effect of extending the reset an extra 100 us, to avoid
-- a pulse being generated or erroneously counted during the period of no signal
-- detect
p_inhibit_first_pulse : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
inhibit_cnt <= (others => '0');
inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then
inhibit_first_pulse <= '0';
end if;
end if;
end if;
end process p_inhibit_first_pulse;
-- Delay inhibit first pulse signal, use this to enable input, thus avoiding
-- internal reset states of conv_common_gw
p_inhibit_first_pulse_d0 : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
inhibit_first_pulse_d0 <= '1';
else
inhibit_first_pulse_d0 <= inhibit_first_pulse;
end if;
end if;
end process p_inhibit_first_pulse_d0;
-- Pulse input valid only after inhibit period is over
pulse_in <= pulse_ttl or pulse_blo when (inhibit_first_pulse_d0 = '0') else
(others => '0');
-- Line inputs for reflection in status register
line_ttl <= not ttl_n_i;
line_invttl <= not inv_n_i;
line_blo <= blo_i;
-- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i;
-- Burst mode functionality is enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
-- *******************************************************************************
-- *******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
-- *******************************************************************************
-- *******************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
cmp_conv_common : conv_common_gw
generic map
(
g_nr_chans => 6,
g_nr_inv_chans => 4,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
g_pgen_fixed_width => true,
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
-- Maximum period supported for 1.2us pulse ~ 4.16kHz, for v3.0 and earlier boards
g_pgen_pperiod_cont => 4800,
g_pgen_gf_len => 1,
-- Golden version disables some features
g_with_pulse_cnt => false,
g_with_pulse_timetag => false,
g_with_man_trig => false,
g_man_trig_pwidth => 24,
g_with_thermometer => false,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
)
port map
(
-- Clocks
clk_20_i => clk_20_i,
clk_125_p_i => clk_125_p_i,
clk_125_n_i => clk_125_n_i,
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o => rst_20_n,
-- Glitch filter active-low enable signal
gf_en_n_i => sw_gp_n_i(0),
-- Burst mode enable signal.
burst_en_n_i => '1', -- Mode disabled for all versions of board
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
pulse_width_sel_n_i => '1', -- long pulses
-- Channel enable
global_ch_oen_o => global_oen_o,
pulse_front_oen_o => ttl_oen_o,
pulse_rear_oen_o => blo_oen_o,
inv_oen_o => inv_oen_o,
-- Front panel channels
pulse_i => pulse_in,
pulse_front_i => pulse_ttl,
pulse_rear_i => pulse_blo,
pulse_o => pulse_out,
-- Inverted pulse I/O
inv_pulse_i_n => inv_pulse_in_n,
inv_pulse_o => inv_pulse_out,
-- Channel leds
led_pulse_o => led_pulse,
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- I2C LED signals -- connect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o => led_i2c,
-- I2C interface
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- VME interface
vme_sysreset_n_i => vme_sysreset_n_i,
vme_ga_i => vme_ga_i,
vme_gap_i => vme_gap_i,
-- SPI interface to on-board flash chip
flash_cs_n_o => flash_cs_n_o,
flash_sclk_o => flash_sclk_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o => dac20_din_o,
dac20_sclk_o => dac20_sclk_o,
dac20_sync_n_o => dac20_sync_n_o,
-- 125 MHz clock generator control
dac125_din_o => dac125_din_o,
dac125_sclk_o => dac125_sclk_o,
dac125_sync_n_o => dac125_sync_n_o,
-- SFP lines
sfp_los_i => sfp_los_i,
sfp_present_i => sfp_mod_def0_i,
sfp_rate_select_o => sfp_rate_select_o,
sfp_sda_b => sfp_mod_def1_b,
sfp_scl_b => sfp_mod_def2_b,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_tx_fault_i => sfp_tx_fault_i,
-- Switch inputs (for readout from converter status register)
sw_gp_i => sw_gp,
sw_other_i => (others => '0'),
-- PCB Version information
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i => line_ttl,
line_inv_i => line_invttl,
line_rear_i => line_blo,
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i => ttlbar_nosig,
line_inv_fs_i => (others => '0'),
line_rear_fs_i => (others => '0'),
-- Thermometer line
thermometer_b => thermometer_b,
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o => led_syserr,
-- Bicolor LED signals
bicolor_led_state_i => bicolor_led_state,
bicolor_led_col_o => bicolor_led_col,
bicolor_led_line_o => bicolor_led_line,
bicolor_led_line_oen_o => bicolor_led_line_oen
);
--============================================================================
-- Channel output logic
--============================================================================
-- TTL and blocking outputs
ttl_o <= pulse_out when sw_ttl = '1' else
not pulse_out;
blo_o <= pulse_out;
-----------------------------------------
-- LED outputs
led_front_n_o <= not led_pulse;
led_front_inv_n_o <= not led_inv_pulse;
led_rear_n_o <= not led_pulse;
-- INV-TTL outputs
inv_pulse_in_n <= inv_n_i;
inv_o <= inv_pulse_out;
--============================================================================
-- Manual reset for blocking power supply
--============================================================================
mr_n_o <= rst_20_n;
--============================================================================
-- External logic for bicolor LED control
--============================================================================
-- Assign bicolor LED lines & columns to outputs
led_wr_ownaddr_i2c_o <= bicolor_led_col(0);
led_wr_gmt_ttl_ttln_o <= bicolor_led_col(1);
led_wr_link_syserror_o <= bicolor_led_col(2);
led_wr_ok_syspw_o <= bicolor_led_col(3);
led_multicast_2_0_o <= bicolor_led_col(4);
led_multicast_3_1_o <= bicolor_led_col(5);
led_ctrl0_o <= bicolor_led_line(0);
led_ctrl1_o <= bicolor_led_line(1);
led_ctrl0_oen_o <= bicolor_led_line_oen(0);
led_ctrl1_oen_o <= bicolor_led_line_oen(1);
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (sw_ttl = '1') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (led_syserr = '1') or
(c_gwvers(7 downto 4) = "0000" ) else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
end architecture arch;
--==============================================================================
-- architecture end
--==============================================================================
top/Release/conv_ttl_blo.vhd
View file @ d6f11be5
......@@ -3,15 +3,8 @@
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--==============================================================================
-- description: RELEASE FIRMWARE
--
-- author: Theodor Stana (t.stana@cern.ch)
-- Carlos-Gil-Soriano
--
-- version: 1.0
--
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
-- components needed in the design and generates the necessary logic for
-- pulse conversion to occur on each channel.
......@@ -21,11 +14,14 @@
--
-- dependencies:
-- general-cores repository [1]
-- conv-common-gw repository [2]
--
-- references:
-- [1] Platform-independent core collection on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- [2] Converter common gateware
-- https://www.ohwr.org/projects/conv-common-gw/repository
-- [3] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
......@@ -41,14 +37,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
-- 05-08-2013 Denia Bouhired Moved processing of inv ttl signals to common gateware module
-- and added output ports for inv pulse LEDs
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
......@@ -83,10 +71,10 @@ entity conv_ttl_blo is
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(5 downto 0);
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
ttl_oen_o : out std_logic;
......@@ -94,18 +82,18 @@ entity conv_ttl_blo is
blo_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);--
ttl_o : out std_logic_vector(5 downto 0);--
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
blo_i : in std_logic_vector(5 downto 0);--
blo_o : out std_logic_vector(5 downto 0);--
blo_i : in std_logic_vector(5 downto 0);
blo_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_n_o : out std_logic_vector(5 downto 0);--
led_front_n_o : out std_logic_vector(5 downto 0);
led_front_inv_n_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
......@@ -186,8 +174,8 @@ architecture arch of conv_ttl_blo is
type t_ttlbar_nosig_cnt is array (c_nr_chans-1 downto 0) of unsigned(10 downto 0);
--Array of constants for temperature model implemented for long long mode
type t_temp_decre_step_lg is array (0 to 14) of integer;
--Array of constants for temperature model implemented for long long mode
type t_temp_decre_step_lg is array (0 to 14) of integer;
--============================================================================
-- Signal declarations
......@@ -198,15 +186,15 @@ architecture arch of conv_ttl_blo is
-- TTL & RS485 signals
signal rs485_fs : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_in : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal inv_pulse_in_n : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_out : std_logic_vector(c_nr_chans-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal inv_pulse_out : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_blo : std_logic_vector(c_nr_chans-1 downto 0);
signal inhibit_first_pulse : std_logic;
signal inhibit_first_pulse_d0 : std_logic;
signal inhibit_cnt : unsigned(10 downto 0);
--Temperature model constantstemp_decre_step_lg
signal temp_decre_step_lg : t_temp_decre_step;
signal temp_decre_step_sh : t_temp_decre_step;
......@@ -229,12 +217,10 @@ architecture arch of conv_ttl_blo is
-- Channel LED signals
signal led_pulse : std_logic_vector(c_nr_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(c_nr_inv_chans-1 downto 0);
signal led_rear : std_logic_vector(c_nr_chans-1 downto 0);
-- I2C LEDs
signal led_i2c : std_logic;
-- System error LED
......@@ -263,7 +249,8 @@ begin
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
-- unnecessary power consumption by the counter
p_ttlbar_nosig : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
......@@ -299,7 +286,7 @@ begin
inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then -- and and_reduce(ttl_n_i)='1') then
if (inhibit_cnt = 1999) then
inhibit_first_pulse <= '0';
end if;
end if;
......@@ -318,7 +305,7 @@ begin
end if;
end if;
end process;
-- Pulse input valid only after inhibit period is over
pulse_in <= (pulse_ttl or pulse_blo) when (inhibit_first_pulse_d0 = '0') else
(others => '0');
......@@ -326,48 +313,43 @@ begin
-- Line inputs for reflection in status register
line_ttl <= not ttl_n_i;
line_invttl <= not inv_n_i;
line_blo <= blo_i;
-- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i;
--Burst mode functionality is enabled for versions 4 and above
-- Burst mode functionality is enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--**************************************************************************
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are physically able to
-- support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--**************************************************************************
--**************************************************************************
--*******************************************************************************
--*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--*******************************************************************************
--*******************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
cmp_conv_common : conv_common_gw
generic map
(
g_nr_chans => 6,
g_nr_inv_chans => 4,
g_board_id => c_board_id,
g_gwvers => c_gwvers,
g_pgen_fixed_width => true,
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_pperiod_cont => 4800,
-- Minimum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191,
-- Minimum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh => 9,
-- Maximum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191,
-- Maximum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh => 9,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step_sh => (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
......@@ -375,7 +357,7 @@ begin
g_burstctrl_1_pulse_temp_rise_sh => x"01388", --5000
g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
......@@ -396,15 +378,15 @@ begin
-- Glitch filter active-low enable signal
gf_en_n_i => sw_gp_n_i(0),
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i => burst_en_n,
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
pulse_width_sel_n_i => sw_gp_n_i(1),
-- Channel enable
......@@ -416,7 +398,7 @@ begin
-- Front panel channels
pulse_i => pulse_in,
pulse_front_i => pulse_ttl,
pulse_rear_i => pulse_blo,
pulse_rear_i => pulse_blo,
pulse_o => pulse_out,
-- Inverted pulse I/O
......@@ -425,11 +407,11 @@ begin
-- Channel leds
led_pulse_o => led_pulse,
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- I2C LED signals -- conect to a bicolor LED of choice
led_inv_pulse_o => led_inv_pulse,
-- I2C LED signals -- connect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o => led_i2c,
......@@ -477,7 +459,7 @@ begin
-- PCB Version information
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
......@@ -518,9 +500,9 @@ begin
-----------------------------------------
-- LED outputs
led_front_n_o <= not led_pulse;
led_front_inv_n_o <= not led_inv_pulse;
led_rear_n_o <= not led_pulse;
-- INV-TTL outputs
......
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