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Conv TTL Blocking - Gateware
Commit d6aa4f02 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Work towards v2.1 gateware 

gencores-suproj: fix bug in wb_i2c_slave
ctblo_pulse_gen.vhd: add pulse_err_o to signal when a pulse is rejected
conv_regs.vhd: add PMISSE and I2C_ERR bits
top-level: implement PMISSE and I2C_ERR bits and change error LED logic
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 46f990ca
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doc/hdlguide/conv-regs.tex
View file @ d6aa4f02
\subsection{Converter board registers} \subsection{Converter board registers}
\label{app:conv-regs} \label{subsec:wbgen:reg}
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
{ {
...@@ -16,30 +16,26 @@ Base address: 0xf{}f{}f{}f{}f{}f{}f{}f ...@@ -16,30 +16,26 @@ Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
\hline \hline
\endfoot \endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\ 0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\ 0x4 & 0xf{}f{}f{}f{}f{}f{}f{}f & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\ 0x8 & 0xf{}f{}f{}f{}f{}f{}f{}f & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\ 0xc & 0xf{}f{}f{}f{}f{}f{}f{}f & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\ 0x10 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\ 0x14 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\ 0x18 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\ 0x1c & 0xf{}f{}f{}f{}f{}f{}f{}f & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\ 0x20 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\ 0x24 & 0xf{}f{}f{}f{}f{}f{}f{}f & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\ 0x28 & 0xf{}f{}f{}f{}f{}f{}f{}f & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\ 0x2c & 0xf{}f{}f{}f{}f{}f{}f{}f & TBMR & Tag Buffer Meta Register\\
0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\ 0x30 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\ 0x34 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\ 0x38 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\ 0x3c & 0xf{}f{}f{}f{}f{}f{}f{}f & TBCSR & Tag Buffer Control and Status Register\\
\end{longtable} \end{longtable}
} }
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\vspace{11pt} \vspace{11pt}
\subsubsection{BIDR -- Board ID Register} \subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -67,7 +63,7 @@ gateware version, the state of the on-board switches and whether an RTM is plugg ...@@ -67,7 +63,7 @@ gateware version, the state of the on-board switches and whether an RTM is plugg
\begin{itemize} \begin{itemize}
\item \begin{small} \item \begin{small}
{\bf {\bf
BITS BIDR
} [\emph{read-only}]: ID register bits } [\emph{read-only}]: ID register bits
\\ \\
Reset value: 0x54424c4f Reset value: 0x54424c4f
...@@ -78,7 +74,6 @@ Reset value: 0x54424c4f ...@@ -78,7 +74,6 @@ Reset value: 0x54424c4f
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{SR -- Status Register} \subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -86,7 +81,7 @@ Reset value: 0x54424c4f ...@@ -86,7 +81,7 @@ Reset value: 0x54424c4f
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\ \multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}PMISSE} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
...@@ -128,7 +123,7 @@ RTM ...@@ -128,7 +123,7 @@ RTM
\item \begin{small} \item \begin{small}
{\bf {\bf
I2C\_WDTO I2C\_WDTO
} [\emph{read/write}]: Communication watchdog timer status } [\emph{read/write}]: I2C communication watchdog timeout error
\\ \\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it 1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small} \end{small}
...@@ -140,12 +135,25 @@ WRPRES ...@@ -140,12 +135,25 @@ WRPRES
1 -- White Rabbit present \\ 0 -- White Rabbit not present 1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle
\end{small}
\item \begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CR -- Control Register} \subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -198,7 +206,6 @@ Write the following sequence to trigger a pulse: \\ 0xde -- ...@@ -198,7 +206,6 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register} \subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\label{app:conv-regs-ch1pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -235,7 +242,6 @@ CH1PCR ...@@ -235,7 +242,6 @@ CH1PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register} \subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\label{app:conv-regs-ch2pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -272,7 +278,6 @@ CH2PCR ...@@ -272,7 +278,6 @@ CH2PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register} \subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\label{app:conv-regs-ch3pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -309,7 +314,6 @@ CH3PCR ...@@ -309,7 +314,6 @@ CH3PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register} \subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\label{app:conv-regs-ch4pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -346,7 +350,6 @@ CH4PCR ...@@ -346,7 +350,6 @@ CH4PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register} \subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\label{app:conv-regs-ch5pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -383,7 +386,6 @@ CH5PCR ...@@ -383,7 +386,6 @@ CH5PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register} \subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\label{app:conv-regs-ch6pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -420,7 +422,6 @@ CH6PCR ...@@ -420,7 +422,6 @@ CH6PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register} \subsubsection{TVLR -- Time Value Low Register}
\label{app:conv-regs-tvlr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -459,7 +460,6 @@ Writing this field resets the internal cycles counter. ...@@ -459,7 +460,6 @@ Writing this field resets the internal cycles counter.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TVHR -- Time Value High Register} \subsubsection{TVHR -- Time Value High Register}
\label{app:conv-regs-tvhr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -498,7 +498,6 @@ Writing this field resets the internal cycles counter. ...@@ -498,7 +498,6 @@ Writing this field resets the internal cycles counter.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBMR -- Tag Buffer Meta Register} \subsubsection{TBMR -- Tag Buffer Meta Register}
\label{app:conv-regs-tbmr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -541,13 +540,9 @@ WRTAG ...@@ -541,13 +540,9 @@ WRTAG
\item \begin{small} \item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBCYR -- Tag Buffer Cycles Register} \subsubsection{TBCYR -- Tag Buffer Cycles Register}
\label{app:conv-regs-tbcyr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -586,7 +581,6 @@ Value of the 8-ns cycles counter when time tag was taken. ...@@ -586,7 +581,6 @@ Value of the 8-ns cycles counter when time tag was taken.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBTLR -- Tag Buffer TAI Low Register} \subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\label{app:conv-regs-tbtlr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -625,9 +619,8 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken. ...@@ -625,9 +619,8 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register} \subsubsection{TBTHR -- Tag Buffer TAI High Register}
\label{app:conv-regs-tbthr}
%\vspace{11pt} \vspace{11pt}
\noindent \noindent
\resizebox{\textwidth}{!}{ \resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
...@@ -664,7 +657,6 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken. ...@@ -664,7 +657,6 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBCSR -- Tag Buffer Control and Status Register} \subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\label{app:conv-regs-tbcsr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -714,7 +706,7 @@ EMPTY ...@@ -714,7 +706,7 @@ EMPTY
\item \begin{small} \item \begin{small}
{\bf {\bf
CLR CLR
} [\emph{write-only}]: Clear tag buffer } [\emph{read/write}]: Clear tag buffer
\\ \\
1 -- clear\\ 0 -- no effect 1 -- clear\\ 0 -- no effect
\end{small} \end{small}
......
general-cores @ 7a8e3f17
Subproject commit 06adc72ad00b288fd509a778db0e1aec65831099 Subproject commit 7a8e3f1768e929e05c261082ad1eb52b324f8e07
modules/Release/conv_regs.vhd
View file @ d6aa4f02
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : conv_regs.vhd -- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb -- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Mar 28 18:31:00 2014 -- Created : Mon Apr 7 16:50:55 2014
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
...@@ -35,16 +35,20 @@ entity conv_regs is ...@@ -35,16 +35,20 @@ entity conv_regs is
reg_sr_switches_i : in std_logic_vector(7 downto 0); reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR' -- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0); reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Communication watchdog timer status' in reg: 'SR' -- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic; reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic; reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic; reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR' -- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic; reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'Missed pulse error bit' in reg: 'SR' -- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_pmiss_o : out std_logic; reg_sr_i2c_err_o : out std_logic;
reg_sr_pmiss_i : in std_logic; reg_sr_i2c_err_i : in std_logic;
reg_sr_pmiss_load_o : out std_logic; reg_sr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic;
reg_sr_pmisse_i : in std_logic;
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR' -- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic; reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic; reg_cr_rst_unlock_i : in std_logic;
...@@ -143,7 +147,8 @@ begin ...@@ -143,7 +147,8 @@ begin
ack_in_progress <= '0'; ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0'; reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0'; reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0'; reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0'; reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0'; reg_cr_mpt_wr_o <= '0';
...@@ -164,7 +169,8 @@ begin ...@@ -164,7 +169,8 @@ begin
if (ack_in_progress = '1') then if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0'; reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0'; reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0'; reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0'; reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0'; reg_cr_mpt_wr_o <= '0';
...@@ -181,7 +187,8 @@ begin ...@@ -181,7 +187,8 @@ begin
ack_in_progress <= '0'; ack_in_progress <= '0';
else else
reg_sr_i2c_wdto_load_o <= '0'; reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0'; reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0'; reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0'; reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0'; reg_cr_mpt_wr_o <= '0';
...@@ -208,15 +215,16 @@ begin ...@@ -208,15 +215,16 @@ begin
when "0001" => when "0001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1'; reg_sr_i2c_wdto_load_o <= '1';
reg_sr_pmiss_load_o <= '1'; reg_sr_i2c_err_load_o <= '1';
reg_sr_pmisse_load_o <= '1';
end if; end if;
rddata_reg(7 downto 0) <= reg_sr_gwvers_i; rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i; rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i; rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i; rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= reg_sr_wrpres_i; rddata_reg(23) <= reg_sr_wrpres_i;
rddata_reg(24) <= reg_sr_pmiss_i; rddata_reg(24) <= reg_sr_i2c_err_i;
rddata_reg(25) <= 'X'; rddata_reg(25) <= reg_sr_pmisse_i;
rddata_reg(26) <= 'X'; rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X'; rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X'; rddata_reg(28) <= 'X';
...@@ -473,11 +481,13 @@ begin ...@@ -473,11 +481,13 @@ begin
-- Gateware version -- Gateware version
-- Status of on-board switches -- Status of on-board switches
-- RTM detection lines~\cite{rtm-det} -- RTM detection lines~\cite{rtm-det}
-- Communication watchdog timer status -- I2C communication watchdog timeout error
reg_sr_i2c_wdto_o <= wrdata_reg(22); reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- White Rabbit present -- White Rabbit present
-- Missed pulse error bit -- I2C communication error
reg_sr_pmiss_o <= wrdata_reg(24); reg_sr_i2c_err_o <= wrdata_reg(24);
-- Pulse missed error
reg_sr_pmisse_o <= wrdata_reg(25);
-- Reset unlock bit -- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0); reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit -- Reset bit
......
modules/Release/conv_regs.wb
View file @ d6aa4f02
...@@ -45,7 +45,6 @@ peripheral { ...@@ -45,7 +45,6 @@ peripheral {
description = "0 -- switch is ON \ description = "0 -- switch is ON \
1 -- switch is OFF \ 1 -- switch is OFF \
bit 0 -- SW1.1 \ bit 0 -- SW1.1 \
bit 1 -- SW1.2 \
... \ ... \
bit 4 -- SW2.1 \ bit 4 -- SW2.1 \
... \ ... \
...@@ -67,7 +66,7 @@ peripheral { ...@@ -67,7 +66,7 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
}; };
field { field {
name = "Communication watchdog timer status"; name = "I2C communication watchdog timeout error";
description = "1 -- timeout occured \ description = "1 -- timeout occured \
0 -- no timeout \ 0 -- no timeout \
This bit can be cleared by writing a '1' to it"; This bit can be cleared by writing a '1' to it";
...@@ -88,10 +87,20 @@ peripheral { ...@@ -88,10 +87,20 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
}; };
field { field {
name = "Missed pulse error bit"; name = "I2C communication error";
description = "1 -- attempted to address non-existing address \
0 -- idle";
prefix = "i2c_err";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Pulse missed error";
description = "1 -- pulse arrived during pulse rejection phase \ description = "1 -- pulse arrived during pulse rejection phase \
0 -- idle"; 0 -- idle";
prefix = "pmiss"; prefix = "pmisse";
type = BIT; type = BIT;
access_dev = READ_WRITE; access_dev = READ_WRITE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
......
modules/Release/ctblo_pulse_gen.vhd
View file @ d6aa4f02
...@@ -72,30 +72,30 @@ entity ctblo_pulse_gen is ...@@ -72,30 +72,30 @@ entity ctblo_pulse_gen is
port port
( (
-- Clock and active-low reset inputs -- Clock and active-low reset inputs
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
-- Glitch filter enable input -- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter) -- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter) -- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic; gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1' -- Enable input, pulse generation is enabled when '1'
en_i : in std_logic; en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater -- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays. -- than internal gate delays.
trig_a_i : in std_logic; trig_a_i : in std_logic;
-- Pulse error output, active-high when a pulse arrives during the -- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- pulse rejection phase -- within a pulse period
pulse_err_o : out std_logic; pulse_err_p_o : out std_logic;
-- Pulse output, active-high -- Pulse output, active-high
-- latency: -- latency:
-- glitch filter disabled: none -- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles -- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic pulse_o : out std_logic
); );
end entity ctblo_pulse_gen; end entity ctblo_pulse_gen;
...@@ -252,7 +252,7 @@ begin ...@@ -252,7 +252,7 @@ begin
pulse_gf_on <= '0'; pulse_gf_on <= '0';
pulse_cnt <= (others => '0'); pulse_cnt <= (others => '0');
inh_fp_gf_on <= '1'; inh_fp_gf_on <= '1';
pulse_err_o <= '0'; pulse_err_p_o <= '0';
elsif (en_i = '1') then elsif (en_i = '1') then
-- On the first cycle after the reset, the pulse channel needs to be -- On the first cycle after the reset, the pulse channel needs to be
-- inhibited when the converter board is in TTL-BAR repetition mode, -- inhibited when the converter board is in TTL-BAR repetition mode,
...@@ -273,9 +273,9 @@ begin ...@@ -273,9 +273,9 @@ begin
-- appropriate input arrives -- appropriate input arrives
--------------------------------------------------------------------- ---------------------------------------------------------------------
when IDLE => when IDLE =>
pulse_cnt <= (others => '0'); pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0'; pulse_gf_off_rst <= '0';
pulse_err_o <= '0'; pulse_err_p_o <= '0';
if (gf_en_n_i = '1') then if (gf_en_n_i = '1') then
if (pulse_gf_off_r_edge_p = '1') then if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF; state <= GEN_GF_OFF;
...@@ -292,24 +292,35 @@ begin ...@@ -292,24 +292,35 @@ begin
-- Extend the generated pulse to the required pulse width. -- Extend the generated pulse to the required pulse width.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when GEN_GF_OFF => when GEN_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1; pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_gen_gf_off) then if (pulse_cnt = c_max_gen_gf_off) then
state <= REJ_GF_OFF; state <= REJ_GF_OFF;
end if; end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
--------------------------------------------------------------------- ---------------------------------------------------------------------
-- REJ_GF_OFF -- REJ_GF_OFF
--------------------------------------------------------------------- ---------------------------------------------------------------------
-- Cut and reject input pulses, to safeguard the output transformers. -- Cut and reject input pulses, to safeguard the output transformers.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when REJ_GF_OFF => when REJ_GF_OFF =>
-- Pulse logic and state change
pulse_gf_off_rst <= '1'; pulse_gf_off_rst <= '1';
pulse_cnt <= pulse_cnt + 1; pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_off) then if (pulse_cnt = c_max_rej_gf_off) then
state <= IDLE; state <= IDLE;
end if; end if;
if (pulse_gf_off_r_edge_p = '1') then
pulse_err_o <= '1'; -- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if; end if;
--------------------------------------------------------------------- ---------------------------------------------------------------------
...@@ -318,25 +329,36 @@ begin ...@@ -318,25 +329,36 @@ begin
-- Start generating the output pulse with the required width. -- Start generating the output pulse with the required width.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when GEN_GF_ON => when GEN_GF_ON =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1; pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1'; pulse_gf_on <= '1';
if (pulse_cnt = c_max_gen_gf_on) then if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON; state <= REJ_GF_ON;
end if; end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
--------------------------------------------------------------------- ---------------------------------------------------------------------
-- REJ_GF_ON -- REJ_GF_ON
--------------------------------------------------------------------- ---------------------------------------------------------------------
-- Stop generating the output pulse and reject incoming pulses. -- Stop generating the output pulse and reject incoming pulses.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when REJ_GF_ON => when REJ_GF_ON =>
-- Pulse logic and state change
pulse_gf_on <= '0'; pulse_gf_on <= '0';
pulse_cnt <= pulse_cnt + 1; pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_on) then if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE; state <= IDLE;
end if; end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then if (trig_gf_on_r_edge_p = '1') then
pulse_err_o <= '1'; pulse_err_p_o <= '1';
end if; end if;
when others => when others =>
......
top/Release/conv_ttl_blo.vhd
View file @ d6aa4f02
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