Commit d6aa4f02 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Work towards v2.1 gateware

gencores-suproj: fix bug in wb_i2c_slave
ctblo_pulse_gen.vhd: add pulse_err_o to signal when a pulse is rejected
conv_regs.vhd: add PMISSE and I2C_ERR bits
top-level: implement PMISSE and I2C_ERR bits and change error LED logic
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 46f990ca
\subsection{Converter board registers}
\label{app:conv-regs}
\label{subsec:wbgen:reg}
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
{
......@@ -16,30 +16,26 @@ Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
0x4 & 0xf{}f{}f{}f{}f{}f{}f{}f & SR & Status Register\\
0x8 & 0xf{}f{}f{}f{}f{}f{}f{}f & CR & Control Register\\
0xc & 0xf{}f{}f{}f{}f{}f{}f{}f & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0xf{}f{}f{}f{}f{}f{}f{}f & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0xf{}f{}f{}f{}f{}f{}f{}f & TVLR & Time Value Low Register\\
0x28 & 0xf{}f{}f{}f{}f{}f{}f{}f & TVHR & Time Value High Register\\
0x2c & 0xf{}f{}f{}f{}f{}f{}f{}f & TBMR & Tag Buffer Meta Register\\
0x30 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0xf{}f{}f{}f{}f{}f{}f{}f & TBCSR & Tag Buffer Control and Status Register\\
\end{longtable}
}
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}
\vspace{11pt}
\noindent
......@@ -67,7 +63,7 @@ gateware version, the state of the on-board switches and whether an RTM is plugg
\begin{itemize}
\item \begin{small}
{\bf
BITS
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
......@@ -78,7 +74,6 @@ Reset value: 0x54424c4f
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}
\vspace{11pt}
\noindent
......@@ -86,7 +81,7 @@ Reset value: 0x54424c4f
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}PMISSE} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
......@@ -128,7 +123,7 @@ RTM
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: Communication watchdog timer status
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
......@@ -140,12 +135,25 @@ WRPRES
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle
\end{small}
\item \begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\vspace{11pt}
\noindent
......@@ -198,7 +206,6 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\end{itemize}
\vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\label{app:conv-regs-ch1pcr}
\vspace{11pt}
\noindent
......@@ -235,7 +242,6 @@ CH1PCR
\end{itemize}
\vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\label{app:conv-regs-ch2pcr}
\vspace{11pt}
\noindent
......@@ -272,7 +278,6 @@ CH2PCR
\end{itemize}
\vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\label{app:conv-regs-ch3pcr}
\vspace{11pt}
\noindent
......@@ -309,7 +314,6 @@ CH3PCR
\end{itemize}
\vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\label{app:conv-regs-ch4pcr}
\vspace{11pt}
\noindent
......@@ -346,7 +350,6 @@ CH4PCR
\end{itemize}
\vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\label{app:conv-regs-ch5pcr}
\vspace{11pt}
\noindent
......@@ -383,7 +386,6 @@ CH5PCR
\end{itemize}
\vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\label{app:conv-regs-ch6pcr}
\vspace{11pt}
\noindent
......@@ -420,7 +422,6 @@ CH6PCR
\end{itemize}
\vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register}
\label{app:conv-regs-tvlr}
\vspace{11pt}
\noindent
......@@ -459,7 +460,6 @@ Writing this field resets the internal cycles counter.
\end{itemize}
\vspace{11pt}
\subsubsection{TVHR -- Time Value High Register}
\label{app:conv-regs-tvhr}
\vspace{11pt}
\noindent
......@@ -498,7 +498,6 @@ Writing this field resets the internal cycles counter.
\end{itemize}
\vspace{11pt}
\subsubsection{TBMR -- Tag Buffer Meta Register}
\label{app:conv-regs-tbmr}
\vspace{11pt}
\noindent
......@@ -541,13 +540,9 @@ WRTAG
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBCYR -- Tag Buffer Cycles Register}
\label{app:conv-regs-tbcyr}
\vspace{11pt}
\noindent
......@@ -586,7 +581,6 @@ Value of the 8-ns cycles counter when time tag was taken.
\end{itemize}
\vspace{11pt}
\subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\label{app:conv-regs-tbtlr}
\vspace{11pt}
\noindent
......@@ -625,9 +619,8 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{itemize}
\vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register}
\label{app:conv-regs-tbthr}
%\vspace{11pt}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
......@@ -664,7 +657,6 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{itemize}
\vspace{11pt}
\subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\label{app:conv-regs-tbcsr}
\vspace{11pt}
\noindent
......@@ -714,7 +706,7 @@ EMPTY
\item \begin{small}
{\bf
CLR
} [\emph{write-only}]: Clear tag buffer
} [\emph{read/write}]: Clear tag buffer
\\
1 -- clear\\ 0 -- no effect
\end{small}
......
general-cores @ 7a8e3f17
Subproject commit 06adc72ad00b288fd509a778db0e1aec65831099
Subproject commit 7a8e3f1768e929e05c261082ad1eb52b324f8e07
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Mar 28 18:31:00 2014
-- Created : Mon Apr 7 16:50:55 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
......@@ -35,16 +35,20 @@ entity conv_regs is
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Communication watchdog timer status' in reg: 'SR'
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'Missed pulse error bit' in reg: 'SR'
reg_sr_pmiss_o : out std_logic;
reg_sr_pmiss_i : in std_logic;
reg_sr_pmiss_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_i2c_err_o : out std_logic;
reg_sr_i2c_err_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic;
reg_sr_pmisse_i : in std_logic;
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
......@@ -143,7 +147,8 @@ begin
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -164,7 +169,8 @@ begin
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -181,7 +187,8 @@ begin
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_pmiss_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
......@@ -208,15 +215,16 @@ begin
when "0001" =>
if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1';
reg_sr_pmiss_load_o <= '1';
reg_sr_i2c_err_load_o <= '1';
reg_sr_pmisse_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= reg_sr_wrpres_i;
rddata_reg(24) <= reg_sr_pmiss_i;
rddata_reg(25) <= 'X';
rddata_reg(24) <= reg_sr_i2c_err_i;
rddata_reg(25) <= reg_sr_pmisse_i;
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
......@@ -473,11 +481,13 @@ begin
-- Gateware version
-- Status of on-board switches
-- RTM detection lines~\cite{rtm-det}
-- Communication watchdog timer status
-- I2C communication watchdog timeout error
reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- White Rabbit present
-- Missed pulse error bit
reg_sr_pmiss_o <= wrdata_reg(24);
-- I2C communication error
reg_sr_i2c_err_o <= wrdata_reg(24);
-- Pulse missed error
reg_sr_pmisse_o <= wrdata_reg(25);
-- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
......
......@@ -45,7 +45,6 @@ peripheral {
description = "0 -- switch is ON \
1 -- switch is OFF \
bit 0 -- SW1.1 \
bit 1 -- SW1.2 \
... \
bit 4 -- SW2.1 \
... \
......@@ -67,7 +66,7 @@ peripheral {
access_bus = READ_ONLY;
};
field {
name = "Communication watchdog timer status";
name = "I2C communication watchdog timeout error";
description = "1 -- timeout occured \
0 -- no timeout \
This bit can be cleared by writing a '1' to it";
......@@ -88,10 +87,20 @@ peripheral {
access_bus = READ_ONLY;
};
field {
name = "Missed pulse error bit";
name = "I2C communication error";
description = "1 -- attempted to address non-existing address \
0 -- idle";
prefix = "i2c_err";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Pulse missed error";
description = "1 -- pulse arrived during pulse rejection phase \
0 -- idle";
prefix = "pmiss";
prefix = "pmisse";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
......
......@@ -72,30 +72,30 @@ entity ctblo_pulse_gen is
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_a_i : in std_logic;
-- Pulse error output, active-high when a pulse arrives during the
-- pulse rejection phase
pulse_err_o : out std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
pulse_o : out std_logic
);
end entity ctblo_pulse_gen;
......@@ -252,7 +252,7 @@ begin
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
inh_fp_gf_on <= '1';
pulse_err_o <= '0';
pulse_err_p_o <= '0';
elsif (en_i = '1') then
-- On the first cycle after the reset, the pulse channel needs to be
-- inhibited when the converter board is in TTL-BAR repetition mode,
......@@ -273,9 +273,9 @@ begin
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0';
pulse_err_o <= '0';
pulse_err_p_o <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF;
......@@ -292,24 +292,35 @@ begin
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_gen_gf_off) then
state <= REJ_GF_OFF;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_OFF
---------------------------------------------------------------------
-- Cut and reject input pulses, to safeguard the output transformers.
---------------------------------------------------------------------
when REJ_GF_OFF =>
-- Pulse logic and state change
pulse_gf_off_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_off) then
state <= IDLE;
end if;
if (pulse_gf_off_r_edge_p = '1') then
pulse_err_o <= '1';
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
......@@ -318,25 +329,36 @@ begin
-- Start generating the output pulse with the required width.
---------------------------------------------------------------------
when GEN_GF_ON =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_ON
---------------------------------------------------------------------
-- Stop generating the output pulse and reject incoming pulses.
---------------------------------------------------------------------
when REJ_GF_ON =>
-- Pulse logic and state change
pulse_gf_on <= '0';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_o <= '1';
pulse_err_p_o <= '1';
end if;
when others =>
......
......@@ -299,30 +299,30 @@ architecture behav of conv_ttl_blo is
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_a_i : in std_logic;
-- Pulse error output, active-high when a pulse arrives during the
-- pulse rejection phase
pulse_err_o : out std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
pulse_o : out std_logic
);
end component ctblo_pulse_gen;
......@@ -364,16 +364,20 @@ architecture behav of conv_ttl_blo is
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'Communication watchdog timer status' in reg: 'SR'
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'Missed pulse error bit' in reg: 'SR'
reg_sr_pmiss_o : out std_logic;
reg_sr_pmiss_i : in std_logic;
reg_sr_pmiss_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_i2c_err_o : out std_logic;
reg_sr_i2c_err_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic;
reg_sr_pmisse_i : in std_logic;
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
......@@ -596,12 +600,12 @@ architecture behav of conv_ttl_blo is
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches_n : std_logic_vector(7 downto 0);
signal wdto_bit : std_logic;
signal wdto_bit_rst : std_logic;
signal wdto_bit_rst_ld : std_logic;
signal pmiss_bit : std_logic;
signal pmiss_bit_rst : std_logic;
signal pmiss_bit_rst_ld : std_logic;
signal i2c_wdto_bit : std_logic;
signal i2c_wdto_bit_rst : std_logic;
signal i2c_wdto_bit_rst_ld : std_logic;
signal pmisse_bit : std_logic;
signal pmisse_bit_rst : std_logic;
signal pmisse_bit_rst_ld : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ch_pcr : t_ch_pcr;
signal ch_pcr_ld : std_logic_vector(g_nr_ttl_chan downto 1);
......@@ -612,6 +616,9 @@ architecture behav of conv_ttl_blo is
signal tvhr : std_logic_vector( 7 downto 0);
signal tvhr_ld : std_logic;
signal wrpres : std_logic;
signal i2c_err_bit : std_logic;
signal i2c_err_bit_rst : std_logic;
signal i2c_err_bit_rst_ld : std_logic;
-- Signals for pulse generation triggers
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
......@@ -623,7 +630,7 @@ architecture behav of conv_ttl_blo is
signal trig_man : std_logic_vector(g_nr_ttl_chan downto 1);
signal pgen_trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal pcnt_trig_p : std_logic_vector(g_nr_ttl_chan downto 1);
signal pmiss : std_logic_vector(g_nr_ttl_chan downto 1);
signal pmiss_p : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
......@@ -652,7 +659,6 @@ architecture behav of conv_ttl_blo is
signal i2c_err_p : std_logic;
signal i2c_wdto_p : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c_err : std_logic;
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(18 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
......@@ -740,7 +746,8 @@ begin
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
-- Instantiate I2C bridge component
--
-- FSM watchdog timeout timer:
-- * consider bit period of 30 us
-- * 10 bits / byte transfer => 300 us
......@@ -829,48 +836,33 @@ begin
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error LED signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk_20_vcxo_i) is
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
led_i2c_err <= '0';
elsif (i2c_err_p = '1') then
led_i2c_err <= '1';
end if;
end if;
end process p_i2c_err_led;
-- Register for the WDTO bit in the SR, cleared by writing a '1'
-- Register for the I2C_WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
wdto_bit <= '0';
i2c_wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
wdto_bit <= '1';
elsif (wdto_bit_rst_ld = '1') and (wdto_bit_rst = '1') then
wdto_bit <= '0';
i2c_wdto_bit <= '1';
elsif (i2c_wdto_bit_rst_ld = '1') and (i2c_wdto_bit_rst = '1') then
i2c_wdto_bit <= '0';
end if;
end if;
end process p_sr_wdto_bit;
-- Register for the PMISS bit in the SR, set by ANY channel missing a pulse,
-- cleared by writing a '1' to it
p_sr_pmiss_bit : process (clk_20_vcxo_i)
-- Register for the I2C_ERR bit in the SR
p_i2c_err_led : process (clk_20_vcxo_i) is
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
pmiss_bit <= '0';
elsif not (pmiss = (pmiss'range => '0')) then
pmiss_bit <= '1';
elsif (pmiss_bit_rst_ld = '1') and (pmiss_bit_rst = '1') then
pmiss_bit <= '0';
i2c_err_bit <= '0';
elsif (i2c_err_p = '1') then
i2c_err_bit <= '1';
elsif (i2c_err_bit_rst_ld = '1') and (i2c_err_bit_rst = '1') then
i2c_err_bit <= '0';
end if;
end if;
end process p_sr_pmiss_bit;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
......@@ -922,13 +914,16 @@ begin
reg_sr_gwvers_i => c_gwvers,
reg_sr_switches_i => switches_n,
reg_sr_rtm_i => rtm_lines,
reg_sr_i2c_wdto_o => wdto_bit_rst,
reg_sr_i2c_wdto_i => wdto_bit,
reg_sr_i2c_wdto_load_o => wdto_bit_rst_ld,
reg_sr_i2c_wdto_o => i2c_wdto_bit_rst,
reg_sr_i2c_wdto_i => i2c_wdto_bit,
reg_sr_i2c_wdto_load_o => i2c_wdto_bit_rst_ld,
reg_sr_wrpres_i => wrpres,
reg_sr_pmiss_o => pmiss_bit_rst,
reg_sr_pmiss_i => pmiss_bit,
reg_sr_pmiss_load_o => pmiss_bit_rst_ld,
reg_sr_i2c_err_o => i2c_err_bit_rst,
reg_sr_i2c_err_i => i2c_err_bit,
reg_sr_i2c_err_load_o => i2c_err_bit_rst_ld,
reg_sr_pmisse_o => pmisse_bit_rst,
reg_sr_pmisse_i => pmisse_bit,
reg_sr_pmisse_load_o => pmisse_bit_rst_ld,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
......@@ -1039,6 +1034,21 @@ begin
end if;
end process p_tbcsr_clr;
-- Register for the PMISS bit in the SR, set by ANY channel missing a pulse,
-- cleared by writing a '1' to it
p_sr_pmisse_bit : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
pmisse_bit <= '0';
elsif not (pmiss_p = (pmiss_p'range => '0')) then
pmisse_bit <= '1';
elsif (pmisse_bit_rst_ld = '1') and (pmisse_bit_rst = '1') then
pmisse_bit <= '0';
end if;
end if;
end process p_sr_pmisse_bit;
--============================================================================
-- Output enable logic
--============================================================================
......@@ -1265,13 +1275,13 @@ begin
)
port map
(
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
en_i => '1',
gf_en_n_i => extra_switch_n_i(1),
trig_a_i => pgen_trig(i),
pulse_err_o => pmiss(i),
pulse_o => pulse_outp(i)
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
en_i => '1',
gf_en_n_i => extra_switch_n_i(1),
trig_a_i => pgen_trig(i),
pulse_err_p_o => pmiss_p(i),
pulse_o => pulse_outp(i)
);
-- Process to flash pulse LED when a pulse is output
......@@ -1405,7 +1415,6 @@ begin
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (led_i2c_err = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
......@@ -1413,7 +1422,9 @@ begin
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
bicolor_led_state(17 downto 16) <= c_LED_RED when (pmisse_bit = '1') or
(i2c_err_bit = '1') or
(i2c_wdto_bit = '1') else
c_LED_OFF;
-- System power
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment