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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
d488b60c
Commit
d488b60c
authored
Sep 29, 2014
by
Theodor-Adrian Stana
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hdl: Use conv-common-gw in golden gateware
parent
3c436187
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5 changed files
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856 additions
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1313 deletions
+856
-1313
conv_ttl_blo.xise
syn/Golden/conv_ttl_blo.xise
+133
-118
flash-release.sh
syn/Golden/flash-release.sh
+4
-0
Manifest.py
top/Golden/Manifest.py
+1
-3
conv_ttl_blo.ucf
top/Golden/conv_ttl_blo.ucf
+374
-398
conv_ttl_blo.vhd
top/Golden/conv_ttl_blo.vhd
+344
-794
No files found.
syn/Golden/conv_ttl_blo.xise
View file @
d488b60c
...
...
@@ -341,360 +341,375 @@
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<bindings/>
...
...
syn/Golden/flash-release.sh
0 → 100755
View file @
d488b60c
#!/bin/bash
xc3sprog
-p
0
-c
xpc flash_load.bit
xc3sprog
-p
0
-c
xpc
-I
conv_ttl_blo.bit:W:0
top/Golden/Manifest.py
View file @
d488b60c
...
...
@@ -5,8 +5,6 @@ files = [
modules
=
{
"local"
:
[
"../../ip_cores/general-cores"
,
"../../modules/Release"
,
"../../modules"
"../../ip_cores/conv-common-gw"
]
}
top/Golden/conv_ttl_blo.ucf
View file @
d488b60c
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#==============================================================================
# CERN (BE-CO-HT)
# UCF defintions file for CONV-TTL-BLO gateware
#==============================================================================
#
# author: Theodor Stana (t.stana@cern.ch)
#
# date of creation: 2013-04-26
#
# version: 1.0
#
# description:
# This file contains the pin definitions for the CONV-TTL-BLO FPGA.
#
# references:
# [1] CONV-TTL-BLO schematics from latest version of project at:
# https://edms.cern.ch/nav/EDA-02446
#
#==============================================================================
# GNU LESSER GENERAL PUBLIC LICENSE
#==============================================================================
# This source file is free software; you can redistribute it and/or modify it
# under the terms of the GNU Lesser General Public License as published by the
# Free Software Foundation; either version 2.1 of the License, or (at your
# option) any later version. This source is distributed in the hope that it
# will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
# See the GNU Lesser General Public License for more details. You should have
# received a copy of the GNU Lesser General Public License along with this
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#==============================================================================
# last changes:
# 2013-04-26 Theodor Stana t.stana@cern.ch File modified
#==============================================================================
# TODO: -
#==============================================================================
#=============================================================================
# CLOCKS AND OUTPUT RESET
#=============================================================================
NET "clk_20_i" LOC = E16;
NET "clk_20_i" TNM_NET = "clk_20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk_20_vcxo_i" 20 MHz HIGH 50 %;
NET "clk_125_p_i" LOC = H12;
NET "clk_125_n_i" LOC = G11;
NET "clk_125_p_i" TNM_NET = "clk_125";
TIMESPEC TSCLK125 = PERIOD "clk_125" 125 MHz HIGH 50 %;
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk125";
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50 %;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
#==============================================================================
# FRONT PANEL
#==============================================================================
#-----------------------------------------------------------------------------
# TTL I/O
#-----------------------------------------------------------------------------
NET "ttl_n_i[0]" LOC = T2;
NET "ttl_n_i[0]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[1]" LOC = U3;
NET "ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[2]" LOC = V5;
NET "ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[3]" LOC = W4;
NET "ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[4]" LOC = T6;
NET "ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "ttl_n_i[5]" LOC = T3;
NET "ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "ttl_o[0]" LOC = C1;
NET "ttl_o[0]" IOSTANDARD = LVCMOS33;
NET "ttl_o[1]" LOC = F2;
NET "ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "ttl_o[2]" LOC = F5;
NET "ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "ttl_o[3]" LOC = H4;
NET "ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "ttl_o[4]" LOC = J4;
NET "ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "ttl_o[5]" LOC = H2;
NET "ttl_o[5]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# INV-TTL I/O
#-----------------------------------------------------------------------------
NET "inv_n_i[0]" LOC = V2;
NET "inv_n_i[0]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[1]" LOC = W3;
NET "inv_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[2]" LOC = Y2;
NET "inv_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_n_i[3]" LOC = AA2;
NET "inv_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_o[0]" LOC = J3;
NET "inv_o[0]" IOSTANDARD = LVCMOS33;
NET "inv_o[1]" LOC = L3;
NET "inv_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_o[2]" LOC = M3;
NET "inv_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_o[3]" LOC = P2;
NET "inv_o[3]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_front_n_o[0]" LOC = H5;
NET "led_front_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[0]" DRIVE = 4;
NET "led_front_n_o[0]" SLEW = QUIETIO;
NET "led_front_n_o[1]" LOC = J6;
NET "led_front_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[1]" DRIVE = 4;
NET "led_front_n_o[1]" SLEW = QUIETIO;
NET "led_front_n_o[2]" LOC = K6;
NET "led_front_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[2]" DRIVE = 4;
NET "led_front_n_o[2]" SLEW = QUIETIO;
NET "led_front_n_o[3]" LOC = K5;
NET "led_front_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[3]" DRIVE = 4;
NET "led_front_n_o[3]" SLEW = QUIETIO;
NET "led_front_n_o[4]" LOC = M7;
NET "led_front_n_o[4]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[4]" DRIVE = 4;
NET "led_front_n_o[4]" SLEW = QUIETIO;
NET "led_front_n_o[5]" LOC = M6;
NET "led_front_n_o[5]" IOSTANDARD = LVCMOS33;
NET "led_front_n_o[5]" DRIVE = 4;
NET "led_front_n_o[5]" SLEW = QUIETIO;
#------------------------------------------------------------------------------
# Status LEDs
#------------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
...
...
@@ -106,260 +164,179 @@ NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
#=============================================================================
# Rear panel signals
#=============================================================================
#-----------------------------------------------------------------------------
# Blocking I/O
#-----------------------------------------------------------------------------
NET "blo_i[0]" LOC = Y9;
NET "blo_i[0]" IOSTANDARD = LVCMOS33;
NET "blo_i[1]" LOC = AA10;
NET "blo_i[1]" IOSTANDARD = LVCMOS33;
NET "blo_i[2]" LOC = W12;
NET "blo_i[2]" IOSTANDARD = LVCMOS33;
NET "blo_i[3]" LOC = AA6;
NET "blo_i[3]" IOSTANDARD = LVCMOS33;
NET "blo_i[4]" LOC = Y7;
NET "blo_i[4]" IOSTANDARD = LVCMOS33;
NET "blo_i[5]" LOC = AA8;
NET "blo_i[5]" IOSTANDARD = LVCMOS33;
NET "blo_o[0]" LOC = W9;
NET "blo_o[0]" IOSTANDARD = LVCMOS33;
NET "blo_o[1]" LOC = T10;
NET "blo_o[1]" IOSTANDARD = LVCMOS33;
NET "blo_o[2]" LOC = V7;
NET "blo_o[2]" IOSTANDARD = LVCMOS33;
NET "blo_o[3]" LOC = U9;
NET "blo_o[3]" IOSTANDARD = LVCMOS33;
NET "blo_o[4]" LOC = T8;
NET "blo_o[4]" IOSTANDARD = LVCMOS33;
NET "blo_o[5]" LOC = R9;
NET "blo_o[5]" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# Channel LEDs
#------------------------------------------------------------------------------
NET "led_rear_n_o[0]" LOC = AB17;
NET "led_rear_n_o[0]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[0]" DRIVE = 4;
NET "led_rear_n_o[0]" SLEW = QUIETIO;
NET "led_rear_n_o[1]" LOC = AB19;
NET "led_rear_n_o[1]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[1]" DRIVE = 4;
NET "led_rear_n_o[1]" SLEW = QUIETIO;
NET "led_rear_n_o[2]" LOC = AA16;
NET "led_rear_n_o[2]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[2]" DRIVE = 4;
NET "led_rear_n_o[2]" SLEW = QUIETIO;
NET "led_rear_n_o[3]" LOC = AA18;
NET "led_rear_n_o[3]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[3]" DRIVE = 4;
NET "led_rear_n_o[3]" SLEW = QUIETIO;
NET "led_rear_n_o[4]" LOC = AB16;
NET "led_rear_n_o[4]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[4]" DRIVE = 4;
NET "led_rear_n_o[4]" SLEW = QUIETIO;
NET "led_rear_n_o[5]" LOC = AB18;
NET "led_rear_n_o[5]" IOSTANDARD = LVCMOS33;
NET "led_rear_n_o[5]" DRIVE = 4;
NET "led_rear_n_o[5]" SLEW = QUIETIO;
#=============================================================================
# Channel enable signals
#=============================================================================
NET "global_oen_o" LOC = R3;
NET "global_oen_o" IOSTANDARD = LVCMOS33;
NET "global_oen_o" DRIVE = 4;
NET "global_oen_o" SLEW = QUIETIO;
NET "ttl_oen_o" LOC = N3;
NET "ttl_oen_o" IOSTANDARD = LVCMOS33;
NET "ttl_oen_o" DRIVE = 4;
NET "ttl_oen_o" SLEW = QUIETIO;
NET "inv_oen_o" LOC = P6;
NET "inv_oen_o" IOSTANDARD = LVCMOS33;
NET "inv_oen_o" DRIVE = 4;
NET "inv_oen_o" SLEW = QUIETIO;
NET "blo_oen_o" LOC = P5;
NET "blo_oen_o" IOSTANDARD = LVCMOS33;
NET "blo_oen_o" DRIVE = 4;
NET "blo_oen_o" SLEW = QUIETIO;
#=============================================================================
# VME CONNECTOR SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# I2C lines
#-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "scl_en_o" LOC = H18;
NET "scl_en_o" IOSTANDARD = LVCMOS33;
NET "scl_en_o" DRIVE = 4;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = LVCMOS33;
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- WHITE RABBIT
##=============================================================================
##-----------------------------------------------------------------------------
##-- Thermo for UID
##-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
NET "sda_en_o" LOC = J19;
NET "sda_en_o" IOSTANDARD = LVCMOS33;
NET "sda_en_o" SLEW = FAST;
NET "sda_en_o" DRIVE = 4;
##-----------------------------------------------------------------------------
##-- DAC control
##-----------------------------------------------------------------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# System reset line
#-----------------------------------------------------------------------------
NET "vme_sysreset_n_i" LOC = L20;
NET "vme_sysreset_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- FPGA MGT lines
##-- Geographical Address
##-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
NET "vme_ga_i[0]" LOC = H20;
NET "vme_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[1]" LOC = J20;
NET "vme_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[2]" LOC = K19;
NET "vme_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[3]" LOC = K20;
NET "vme_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[4]" LOC = L19;
NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "vme_gap_i" LOC = H19;
NET "vme_gap_i" IOSTANDARD = LVCMOS33;
#=============================================================================
# WHITE RABBIT
#=============================================================================
#-----------------------------------------------------------------------------
# DAC control
#-----------------------------------------------------------------------------
NET "dac20_din_o" LOC = AB14;
NET "dac20_din_o" IOSTANDARD = LVCMOS33;
NET "dac20_sclk_o" LOC = AA14;
NET "dac20_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac20_sync_n_o" LOC = AB15;
NET "dac20_sync_n_o" IOSTANDARD = LVCMOS33;
NET "dac125_din_o" LOC = W14;
NET "dac125_din_o" IOSTANDARD = LVCMOS33;
NET "dac125_sclk_o" LOC = Y14;
NET "dac125_sclk_o" IOSTANDARD = LVCMOS33;
NET "dac125_sync_n_o" LOC = W13;
NET "dac125_sync_n_o" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# SFP connection
#-----------------------------------------------------------------------------
NET "sfp_los_i" LOC = G3;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_i" LOC = K8;
NET "sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_o" LOC = C4;
NET "sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b" LOC = G4;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b" LOC = F3;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o" LOC = E4;
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" LOC = D2;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# FPGA MGT lines
#-----------------------------------------------------------------------------
#NET "mgt_clk0_p_i" LOC = A10;
#NET "mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
...
...
@@ -367,89 +344,88 @@ NET "fpga_sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
##=============================================================================
##-- ADDITIONAL PINS
##=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = LVCMOS33;
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
#=============================================================================
# OTHER SIGNALS
#=============================================================================
#-----------------------------------------------------------------------------
# One-wire thermometer data signal
#-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
#-----------------------------------------------------------------------------
# General-purpose switches
#-----------------------------------------------------------------------------
NET "sw_gp_n_i[0]" LOC = F22;
NET "sw_gp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[1]" LOC = G22;
NET "sw_gp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[2]" LOC = H21;
NET "sw_gp_n_i[2]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[3]" LOC = H22;
NET "sw_gp_n_i[3]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[4]" LOC = J22;
NET "sw_gp_n_i[4]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[5]" LOC = K21;
NET "sw_gp_n_i[5]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[6]" LOC = K22;
NET "sw_gp_n_i[6]" IOSTANDARD = LVCMOS33;
NET "sw_gp_n_i[7]" LOC = L22;
NET "sw_gp_n_i[7]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# RTM detection lines
#-----------------------------------------------------------------------------
NET "rtmm_i[0]" LOC = V21;
NET "rtmm_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[1]" LOC = V22;
NET "rtmm_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmm_i[2]" LOC = U22;
NET "rtmm_i[2]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[0]" LOC = W22;
NET "rtmp_i[0]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[1]" LOC = Y22;
NET "rtmp_i[1]" IOSTANDARD = LVCMOS33;
NET "rtmp_i[2]" LOC = Y21;
NET "rtmp_i[2]" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# Flash memory
#-----------------------------------------------------------------------------
NET "flash_sclk_o" LOC = Y20;
NET "flash_sclk_o" IOSTANDARD = LVCMOS33;
NET "flash_cs_n_o" LOC = AA3;
NET "flash_cs_n_o" IOSTANDARD = LVCMOS33;
NET "flash_miso_i" LOC = AA20;
NET "flash_miso_i" IOSTANDARD = LVCMOS33;
NET "flash_mosi_o" LOC = AB20;
NET "flash_mosi_o" IOSTANDARD = LVCMOS33;
##----------------------------------------------------------------------------
## General purpose
##----------------------------------------------------------------------------
# NET "dbg_header_n_o[0]" LOC = F15;
# NET "dbg_header_n_o[0]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[1]" LOC = F16;
# NET "dbg_header_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[2]" LOC = F17;
# NET "dbg_header_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[3]" LOC = F14;
# NET "dbg_header_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[4]" LOC = H14;
# NET "dbg_header_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_o[5]" LOC = H13;
# NET "dbg_header_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[0]" LOC = A17;
# NET "dbg_header_n_i[0]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[1]" LOC = A18;
# NET "dbg_header_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[2]" LOC = B18;
# NET "dbg_header_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[3]" LOC = A19;
# NET "dbg_header_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[4]" LOC = A20;
# NET "dbg_header_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "dbg_header_n_i[5]" LOC = B20;
# NET "dbg_header_n_i[5]" IOSTANDARD = "LVCMOS33";
top/Golden/conv_ttl_blo.vhd
View file @
d488b60c
...
...
@@ -7,7 +7,7 @@
-- author: Theodor Stana (t.stana@cern.ch)
-- Carlos-Gil-Soriano
--
-- version:
0.0 -- golden firmware version
-- version:
1.0
--
-- description:
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
...
...
@@ -45,386 +45,176 @@
-- TODO: -
--==============================================================================
library
ieee
;
library
unisim
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
unisim
.
vcomponents
.
all
;
use
work
.
bicolor_led_ctrl_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
gencores_pkg
.
all
;
use
work
.
wishbone_pkg
.
all
;
use
work
.
conv_common_gw_pkg
.
all
;
entity
conv_ttl_blo
is
generic
(
g_nr_ttl_chan
:
natural
:
=
6
;
g_nr_inv_chan
:
natural
:
=
4
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk20_vcxo_i
:
in
std_logic
;
-- 125 MHz from clock generator
fpga_clk_p_i
:
in
std_logic
;
fpga_clk_n_i
:
in
std_logic
;
-- LEDs
led_ctrl0_o
:
out
std_logic
;
led_ctrl0_oen_o
:
out
std_logic
;
led_ctrl1_o
:
out
std_logic
;
led_ctrl1_oen_o
:
out
std_logic
;
led_multicast_2_0_o
:
out
std_logic
;
led_multicast_3_1_o
:
out
std_logic
;
led_wr_gmt_ttl_ttln_o
:
out
std_logic
;
led_wr_link_syserror_o
:
out
std_logic
;
led_wr_ok_syspw_o
:
out
std_logic
;
led_wr_ownaddr_i2c_o
:
out
std_logic
;
-- I/Os for pulses
pulse_front_led_n_o
:
out
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
pulse_rear_led_n_o
:
out
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
fpga_input_ttl_n_i
:
in
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
fpga_out_ttl_o
:
out
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
fpga_blo_in_i
:
in
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
fpga_trig_blo_o
:
out
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
inv_in_n_i
:
in
std_logic_vector
(
g_nr_inv_chan
downto
1
);
inv_out_o
:
out
std_logic_vector
(
g_nr_inv_chan
downto
1
);
-- Output enable lines
fpga_oe_o
:
out
std_logic
;
fpga_blo_oe_o
:
out
std_logic
;
fpga_trig_ttl_oe_o
:
out
std_logic
;
fpga_inv_oe_o
:
out
std_logic
;
--TTL/INV_TTL_N
ttl_switch_n_i
:
in
std_logic
;
extra_switch_n_i
:
in
std_logic_vector
(
7
downto
1
);
-- Lines for the i2c_slave
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
scl_oe_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
sda_oe_o
:
out
std_logic
;
fpga_ga_i
:
in
std_logic_vector
(
4
downto
0
);
fpga_gap_i
:
in
std_logic
;
-- Flash memory lines
fpga_prom_cclk_o
:
out
std_logic
;
fpga_prom_cso_b_n_o
:
out
std_logic
;
fpga_prom_mosi_o
:
out
std_logic
;
fpga_prom_miso_i
:
in
std_logic
;
-- Blocking power supply reset line
mr_n_o
:
out
std_logic
;
-- Thermometer line
thermometer_b
:
inout
std_logic
;
clk_20_i
:
in
std_logic
;
clk_125_p_i
:
in
std_logic
;
clk_125_n_i
:
in
std_logic
;
-- Active-low reset for blocking power supply
mr_n_o
:
out
std_logic
;
-- I2C interface
scl_i
:
in
std_logic
;
scl_o
:
out
std_logic
;
scl_en_o
:
out
std_logic
;
sda_i
:
in
std_logic
;
sda_o
:
out
std_logic
;
sda_en_o
:
out
std_logic
;
-- VME interface
vme_sysreset_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
-- Channel enable
global_oen_o
:
out
std_logic
;
ttl_oen_o
:
out
std_logic
;
inv_oen_o
:
out
std_logic
;
blo_oen_o
:
out
std_logic
;
-- Front panel channels
ttl_n_i
:
in
std_logic_vector
(
5
downto
0
);
ttl_o
:
out
std_logic_vector
(
5
downto
0
);
inv_n_i
:
in
std_logic_vector
(
3
downto
0
);
inv_o
:
out
std_logic_vector
(
3
downto
0
);
-- Rear panel channels
blo_i
:
in
std_logic_vector
(
5
downto
0
);
blo_o
:
out
std_logic_vector
(
5
downto
0
);
-- Channel leds
led_front_n_o
:
out
std_logic_vector
(
5
downto
0
);
led_rear_n_o
:
out
std_logic_vector
(
5
downto
0
);
-- SPI interface to on-board flash chip
flash_cs_n_o
:
out
std_logic
;
flash_sclk_o
:
out
std_logic
;
flash_mosi_o
:
out
std_logic
;
flash_miso_i
:
in
std_logic
;
-- PLL DACs
--
DAC1:
20 MHz VCXO control
fpga_plldac1_din_o
:
out
std_logic
;
fpga_plldac1_sclk_o
:
out
std_logic
;
fpga_plldac1_sync_n_o
:
out
std_logic
;
--
DAC2:
125 MHz clock generator control
fpga_plldac2_din_o
:
out
std_logic
;
fpga_plldac2_sclk_o
:
out
std_logic
;
fpga_plldac2_sync_n_o
:
out
std_logic
;
-- 20 MHz VCXO control
dac20_din_o
:
out
std_logic
;
dac20_sclk_o
:
out
std_logic
;
dac20_sync_n_o
:
out
std_logic
;
-- 125 MHz clock generator control
dac125_din_o
:
out
std_logic
;
dac125_sclk_o
:
out
std_logic
;
dac125_sync_n_o
:
out
std_logic
;
-- SFP lines
fpga_sfp_los_i
:
in
std_logic
;
fpga_sfp_mod_def0_i
:
in
std_logic
;
fpga_sfp_rate_select_o
:
out
std_logic
;
fpga_sfp_mod_def1_b
:
inout
std_logic
;
fpga_sfp_mod_def2_b
:
inout
std_logic
;
fpga_sfp_tx_disable_o
:
out
std_logic
;
fpga_sfp_tx_fault_i
:
in
std_logic
;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i
:
in
std_logic_vector
(
2
downto
0
);
fpga_rtmp_n_i
:
in
std_logic_vector
(
2
downto
0
)
sfp_los_i
:
in
std_logic
;
sfp_mod_def0_i
:
in
std_logic
;
sfp_rate_select_o
:
out
std_logic
;
sfp_mod_def1_b
:
inout
std_logic
;
sfp_mod_def2_b
:
inout
std_logic
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
;
-- Thermometer data port
thermometer_b
:
inout
std_logic
;
-- Switches
sw_gp_n_i
:
in
std_logic_vector
(
7
downto
0
);
-- RTM lines
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
-- Front panel bicolor LEDs
led_ctrl0_o
:
out
std_logic
;
led_ctrl0_oen_o
:
out
std_logic
;
led_ctrl1_o
:
out
std_logic
;
led_ctrl1_oen_o
:
out
std_logic
;
led_multicast_2_0_o
:
out
std_logic
;
led_multicast_3_1_o
:
out
std_logic
;
led_wr_gmt_ttl_ttln_o
:
out
std_logic
;
led_wr_link_syserror_o
:
out
std_logic
;
led_wr_ok_syspw_o
:
out
std_logic
;
led_wr_ownaddr_i2c_o
:
out
std_logic
);
end
conv_ttl_blo
;
end
entity
conv_ttl_blo
;
architecture
behav
of
conv_ttl_blo
is
--============================================================================
-- Type declarations
--============================================================================
type
t_ttlbar_nosig_cnt
is
array
(
1
to
g_nr_ttl_chan
)
of
unsigned
(
10
downto
0
);
type
t_pulse_led_cnt
is
array
(
1
to
g_nr_ttl_chan
)
of
unsigned
(
18
downto
0
);
architecture
arch
of
conv_ttl_blo
is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of repetition channels
constant
c_nr_chans
:
integer
:
=
6
;
constant
c_nr_inv_chans
:
integer
:
=
4
;
-- Number of bicolor LED lines & columns
constant
c_bicolor_led_lines
:
integer
:
=
2
;
constant
c_bicolor_led_cols
:
integer
:
=
6
;
-- Board ID - ASCII string "TBLO"
constant
c_board_id
:
std_logic_vector
(
31
downto
0
)
:
=
x"54424c4f"
;
-- Firmware version
-- - format: M.m
-- - M: major version hex number (e.g. 1)
-- - m: minor version hex number (e.g. 13)
-- - example: first major release v1.0 c_fwvers = x"10";
-- next minor release v1.1 c_fwvers = x"11";
-- 13 minor releases later v1.14 c_fwvers = x"1e";
-- next major release v2.0 c_fwvers = x"20";
-- - version 0.1 is golden firmware version for MultiBoot fallback
constant
c_fwvers
:
std_logic_vector
(
7
downto
0
)
:
=
x"01"
;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
constant
c_nr_slaves
:
natural
:
=
2
;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- CONV_REGS [000-040]
-- MULTIBOOT [040-080]
-----------------------------------------
-- slave order definitions
constant
c_slv_conv_regs
:
natural
:
=
0
;
constant
c_slv_multiboot
:
natural
:
=
1
;
-- base address definitions
constant
c_addr_conv_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_multiboot
:
t_wishbone_address
:
=
x"00000040"
;
-- address mask definitions
constant
c_mask_conv_regs
:
t_wishbone_address
:
=
x"00000FC0"
;
constant
c_mask_multiboot
:
t_wishbone_address
:
=
x"00000FC0"
;
-- addresses constant for Wishbone crossbar
constant
c_addresses
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_conv_regs
=>
c_addr_conv_regs
,
c_slv_multiboot
=>
c_addr_multiboot
);
-- masks constant for Wishbone crossbar
constant
c_masks
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_conv_regs
=>
c_mask_conv_regs
,
c_slv_multiboot
=>
c_mask_multiboot
);
------------------------------------------------------------------------------
-- Pulse generator constants
------------------------------------------------------------------------------
constant
c_pulse_gen_pwidth
:
positive
:
=
24
;
constant
c_pulse_gen_duty_cycle_div
:
positive
:
=
200
;
constant
c_pulse_gen_gf_len
:
positive
:
=
1
;
-- Gateware version
constant
c_gwvers
:
std_logic_vector
(
7
downto
0
)
:
=
x"02"
;
--============================================================================
--
Component
declarations
--
Type
declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component
reset_gen
is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time
:
positive
:
=
2
_
000
_
000
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
rst_n_o
:
out
std_logic
);
end
component
reset_gen
;
-- Pulse generator component
-- (use: output pulse generation, pulse status LEDs)
component
ctblo_pulse_gen
is
generic
(
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth
:
natural
range
20
to
40
:
=
24
;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div
:
natural
:
=
5
);
port
(
-- Clock and active-low reset inputs
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i
:
in
std_logic
;
-- Enable input, pulse generation is enabled when '1'
en_i
:
in
std_logic
;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i
:
in
std_logic
;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o
:
out
std_logic
;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o
:
out
std_logic
);
end
component
ctblo_pulse_gen
;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component
rtm_detector
is
port
(
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
rtmm_ok_o
:
out
std_logic
;
rtmp_ok_o
:
out
std_logic
);
end
component
rtm_detector
;
-- Converter board control registers
component
conv_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
reg_id_bits_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
reg_sr_fwvers_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
reg_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
reg_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
reg_sr_i2c_wdto_o
:
out
std_logic
;
reg_sr_i2c_wdto_i
:
in
std_logic
;
reg_sr_i2c_wdto_load_o
:
out
std_logic
;
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control Register'
reg_cr_rst_unlock_o
:
out
std_logic
;
reg_cr_rst_unlock_i
:
in
std_logic
;
reg_cr_rst_unlock_load_o
:
out
std_logic
;
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o
:
out
std_logic
;
reg_cr_rst_i
:
in
std_logic
;
reg_cr_rst_load_o
:
out
std_logic
);
end
component
conv_regs
;
-- MultiBoot component
-- use: remotely reprogram the FPGA
component
wb_xil_multiboot
is
port
(
-- Clock and reset input ports
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Wishbone ports
wbs_i
:
in
t_wishbone_slave_in
;
wbs_o
:
out
t_wishbone_slave_out
;
-- SPI ports
spi_cs_n_o
:
out
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
);
end
component
wb_xil_multiboot
;
type
t_ttlbar_nosig_cnt
is
array
(
c_nr_chans
-1
downto
0
)
of
unsigned
(
10
downto
0
);
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signals
signal
rst_n
:
std_logic
;
signal
rst_unlock
:
std_logic
;
signal
rst_unlock_bit
:
std_logic
;
signal
rst_unlock_bit_ld
:
std_logic
;
signal
rst_bit
:
std_logic
;
signal
rst_bit_ld
:
std_logic
;
signal
rst_fr_reg
:
std_logic
;
-- RTM detection signals
signal
rtmm
,
rtmp
:
std_logic_vector
(
2
downto
0
);
signal
rtmm_ok
,
rtmp_ok
:
std_logic
;
-- Signals to/from converter system registers component
signal
rtm_lines
:
std_logic_vector
(
5
downto
0
);
signal
switches_n
:
std_logic_vector
(
7
downto
0
);
signal
wdto_bit
:
std_logic
;
signal
wdto_bit_rst
:
std_logic
;
signal
wdto_bit_rst_ld
:
std_logic
;
-- Signals for pulse generation triggers
signal
trig_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_inv
:
std_logic_vector
(
g_nr_inv_chan
downto
1
);
signal
trig_ttl_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_blo_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced_edge
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_degl
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_chan
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- TTL-BAR lack of signal counter
signal
ttlbar_nosig_cnt
:
t_ttlbar_nosig_cnt
;
signal
ttlbar_nosig_n
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- Temporary signal for blocking and TTL pulse outputs
signal
pulse_outp
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_outp_d0
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_outp_r_edge_p
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
blo_ch_en
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- Pulse status LED signals
signal
pulse_leds
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pulse_led_cnt
:
t_pulse_led_cnt
;
-- Output enable signals
signal
oe
,
ttl_oe
:
std_logic
;
signal
blo_oe
,
inv_oe
:
std_logic
;
-- Signal for controlling the bicolor LED matrix
signal
bicolor_led_state
:
std_logic_vector
(
23
downto
0
);
-- Wishbone crossbar signals
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_master_in
:
t_wishbone_master_in_array
(
c_nr_slaves
-
1
downto
0
);
signal
xbar_master_out
:
t_wishbone_master_out_array
(
c_nr_slaves
-
1
downto
0
);
-- I2C bridge signals
signal
i2c_tip
:
std_logic
;
signal
i2c_err_p
:
std_logic
;
signal
i2c_wdto_p
:
std_logic
;
signal
i2c_addr
:
std_logic_vector
(
6
downto
0
);
signal
led_i2c_err
:
std_logic
;
signal
led_i2c
:
std_logic
;
signal
led_i2c_clkdiv
:
unsigned
(
18
downto
0
);
signal
led_i2c_cnt
:
unsigned
(
2
downto
0
);
signal
led_i2c_blink
:
std_logic
;
-- Reset signal
signal
rst_20_n
:
std_logic
;
-- TTL & RS485 signals
signal
rs485_fs
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
pulse_in
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
pulse_out
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
pulse_ttl
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
pulse_blo
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
inhibit_first_pulse
:
std_logic
;
signal
inhibit_first_pulse_d0
:
std_logic
;
signal
inhibit_cnt
:
unsigned
(
10
downto
0
);
-- Line signals -- for reflection in line status register of conv_common_gw
signal
line_ttl
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
line_invttl
:
std_logic_vector
(
3
downto
0
);
signal
line_blo
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
-- Switch signals (for inverting switch inputs to the common g/w)
signal
sw_ttl
:
std_logic
;
signal
sw_gp
:
std_logic_vector
(
7
downto
0
);
-- No signal on TTL-BAR
signal
ttlbar_nosig_cnt
:
t_ttlbar_nosig_cnt
;
signal
ttlbar_nosig
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
-- Channel LED signals
signal
led_pulse
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
led_rear
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
-- I2C LEDs
signal
led_i2c
:
std_logic
;
-- System error LED
signal
led_syserr
:
std_logic
;
-- Bicolor LED signals
signal
bicolor_led_state
:
std_logic_vector
(
2
*
c_bicolor_led_cols
*
c_bicolor_led_lines
-1
downto
0
);
signal
bicolor_led_col
:
std_logic_vector
(
c_bicolor_led_cols
-1
downto
0
);
signal
bicolor_led_line
:
std_logic_vector
(
c_bicolor_led_lines
-1
downto
0
);
signal
bicolor_led_line_oen
:
std_logic_vector
(
c_bicolor_led_lines
-1
downto
0
);
--==============================================================================
-- architecture begin
...
...
@@ -432,414 +222,236 @@ architecture behav of conv_ttl_blo is
begin
--============================================================================
--
Internal and external reset generation
--
Channel input logic
--============================================================================
-- Configure reset generator for 100ms power-on reset
cmp_reset_gen
:
reset_gen
generic
map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time
=>
2
*
(
10
**
6
)
)
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_i
=>
rst_fr_reg
,
rst_n_o
=>
rst_n
);
mr_n_o
<=
rst_n
;
-- TTL switch
sw_ttl
<=
not
sw_gp_n_i
(
7
);
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr
<=
"10"
&
fpga_ga_i
;
-- Instantiate I2C bridge component
-- The "no signal detect" block
--
-- FSM watchdog timeout timer:
-- * consider bit period of 30 us
-- * 10 bits / byte transfer => 300 us
-- * 40 bytes in one transfer => 12000 us
-- * clk_i period = 50 ns => g_fsm_wdt = 12000 us / 50 ns = 240000
-- * multiply by two for extra safety => g_fsm_wdt = 480000
-- * Time to watchdog timeout: 480000 * 50ns = 24 ms
cmp_i2c_bridge
:
wb_i2c_bridge
generic
map
(
g_fsm_wdt
=>
480000
)
port
map
(
-- Clock, reset
clk_i
=>
clk20_vcxo_i
,
rst_n_i
=>
rst_n
,
-- I2C lines
scl_i
=>
scl_i
,
scl_o
=>
scl_o
,
scl_en_o
=>
scl_oe_o
,
sda_i
=>
sda_i
,
sda_o
=>
sda_o
,
sda_en_o
=>
sda_oe_o
,
-- I2C address and status
i2c_addr_i
=>
i2c_addr
,
-- TIP and ERR outputs
tip_o
=>
i2c_tip
,
err_p_o
=>
i2c_err_p
,
wdto_p_o
=>
i2c_wdto_p
,
-- Wishbone master signals
wbm_stb_o
=>
xbar_slave_in
(
0
)
.
stb
,
wbm_cyc_o
=>
xbar_slave_in
(
0
)
.
cyc
,
wbm_sel_o
=>
xbar_slave_in
(
0
)
.
sel
,
wbm_we_o
=>
xbar_slave_in
(
0
)
.
we
,
wbm_dat_i
=>
xbar_slave_out
(
0
)
.
dat
,
wbm_dat_o
=>
xbar_slave_in
(
0
)
.
dat
,
wbm_adr_o
=>
xbar_slave_in
(
0
)
.
adr
,
wbm_ack_i
=>
xbar_slave_out
(
0
)
.
ack
,
wbm_rty_i
=>
xbar_slave_out
(
0
)
.
rty
,
wbm_err_i
=>
xbar_slave_out
(
0
)
.
err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink
:
process
(
clk20_vcxo_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
led_i2c_clkdiv
<=
(
others
=>
'0'
);
led_i2c_cnt
<=
(
others
=>
'0'
);
led_i2c
<=
'0'
;
led_i2c_blink
<=
'0'
;
else
case
led_i2c_blink
is
when
'0'
=>
led_i2c
<=
'0'
;
if
(
i2c_tip
=
'1'
)
then
led_i2c_blink
<=
'1'
;
end
if
;
when
'1'
=>
led_i2c_clkdiv
<=
led_i2c_clkdiv
+
1
;
if
(
led_i2c_clkdiv
=
399999
)
then
led_i2c_clkdiv
<=
(
others
=>
'0'
);
led_i2c_cnt
<=
led_i2c_cnt
+
1
;
led_i2c
<=
not
led_i2c
;
if
(
led_i2c_cnt
=
7
)
then
led_i2c_cnt
<=
(
others
=>
'0'
);
led_i2c_blink
<=
'0'
;
end
if
;
end
if
;
when
others
=>
led_i2c_blink
<=
'0'
;
end
case
;
end
if
;
end
if
;
end
process
p_i2c_blink
;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error LED signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led
:
process
(
clk20_vcxo_i
)
is
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
led_i2c_err
<=
'0'
;
elsif
(
i2c_err_p
=
'1'
)
then
led_i2c_err
<=
'1'
;
end
if
;
end
if
;
end
process
p_i2c_err_led
;
-- Register for the WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit
:
process
(
clk20_vcxo_i
)
-- If the signal line is high for 100 us, the ttlbar_nosig lines disable
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
p_ttlbar_nosig
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
wdto_bit
<=
'0'
;
elsif
(
i2c_wdto_p
=
'1'
)
then
wdto_bit
<=
'1'
;
elsif
(
wdto_bit_rst_ld
=
'1'
)
and
(
wdto_bit_rst
=
'1'
)
then
wdto_bit
<=
'0'
;
end
if
;
if
rising_edge
(
clk_20_i
)
then
for
i
in
0
to
c_nr_chans
-1
loop
if
(
rst_20_n
=
'0'
)
or
(
ttl_n_i
(
i
)
=
'0'
)
then
ttlbar_nosig
(
i
)
<=
'0'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
elsif
(
sw_ttl
=
'0'
)
then
ttlbar_nosig_cnt
(
i
)
<=
ttlbar_nosig_cnt
(
i
)
+
1
;
if
(
ttlbar_nosig_cnt
(
i
)
=
1999
)
then
ttlbar_nosig
(
i
)
<=
'1'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
loop
;
end
if
;
end
process
p_
sr_wdto_bit
;
end
process
p_
ttlbar_nosig
;
--
============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
--
TTL and blocking inputs
pulse_ttl
<=
not
ttl_n_i
when
sw_ttl
=
'1'
else
ttl_n_i
and
(
not
ttlbar_nosig
);
cmp_wb_crossbar
:
xwb_crossbar
generic
map
(
g_num_masters
=>
c_nr_masters
,
g_num_slaves
=>
c_nr_slaves
,
g_registered
=>
false
,
g_address
=>
c_addresses
,
g_mask
=>
c_masks
)
port
map
(
clk_sys_i
=>
clk20_vcxo_i
,
rst_n_i
=>
rst_n
,
slave_i
=>
xbar_slave_in
,
slave_o
=>
xbar_slave_out
,
master_i
=>
xbar_master_in
,
master_o
=>
xbar_master_out
);
--============================================================================
-- Converter board registers
--============================================================================
-- Set SWITCH and RTM fields
switches_n
<=
ttl_switch_n_i
&
extra_switch_n_i
(
7
downto
1
);
rtm_lines
<=
rtmp
&
rtmm
;
-- Then, instantiate the component
cmp_conv_regs
:
conv_regs
port
map
(
rst_n_i
=>
rst_n
,
clk_sys_i
=>
clk20_vcxo_i
,
wb_adr_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
stall
,
reg_id_bits_i
=>
c_board_id
,
reg_sr_fwvers_i
=>
c_fwvers
,
reg_sr_switches_i
=>
switches_n
,
reg_sr_rtm_i
=>
rtm_lines
,
reg_sr_i2c_wdto_o
=>
wdto_bit_rst
,
reg_sr_i2c_wdto_i
=>
wdto_bit
,
reg_sr_i2c_wdto_load_o
=>
wdto_bit_rst_ld
,
reg_cr_rst_unlock_o
=>
rst_unlock_bit
,
reg_cr_rst_unlock_i
=>
rst_unlock
,
reg_cr_rst_unlock_load_o
=>
rst_unlock_bit_ld
,
reg_cr_rst_o
=>
rst_bit
,
reg_cr_rst_i
=>
rst_fr_reg
,
reg_cr_rst_load_o
=>
rst_bit_ld
);
pulse_blo
<=
blo_i
;
-- Implement the RST_UNLOCK bit
p_rst_unlock
:
process
(
clk20_vcxo_i
)
-- This process has the effect of extending the reset an extra 100 us, to avoid
-- a pulse being generated or erroneously counted during the period of no signal
-- detect
p_inhibit_first_pulse
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk
20_vcxo
_i
)
then
if
(
rst_n
=
'0'
)
then
rst_unlock
<=
'0'
;
elsif
(
rst_unlock_bit_ld
=
'1'
)
then
if
(
rst_unlock_bit
=
'1'
)
then
rst_unlock
<=
'1'
;
else
rst_unlock
<=
'0'
;
if
rising_edge
(
clk
_20
_i
)
then
if
(
rst_
20_
n
=
'0'
)
then
inhibit_cnt
<=
(
others
=>
'0'
)
;
inhibit_first_pulse
<=
'1'
;
elsif
(
inhibit_first_pulse
=
'1'
)
then
inhibit_cnt
<=
inhibit_cnt
+
1
;
if
(
inhibit_cnt
=
1999
)
then
inhibit_first_pulse
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
p_
rst_unlock
;
end
process
p_
inhibit_first_pulse
;
--
Implement the reset bit register
--
The register can only be set when the RST_UNLOCK bit is '1'.
p_
rst_fr_reg
:
process
(
clk20_vcxo
_i
)
--
Delay inhibit first pulse signal, use this to enable input, thus avoiding
--
internal reset states of conv_common_gw
p_
inhibit_first_pulse_d0
:
process
(
clk_20
_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
rst_fr_reg
<=
'0'
;
elsif
(
rst_bit_ld
=
'1'
)
and
(
rst_bit
=
'1'
)
and
(
rst_unlock
=
'1'
)
then
rst_fr_reg
<=
'1'
;
if
rising_edge
(
clk_20_i
)
then
if
(
rst_20_n
=
'0'
)
then
inhibit_first_pulse_d0
<=
'1'
;
else
rst_fr_reg
<=
'0'
;
inhibit_first_pulse_d0
<=
inhibit_first_pulse
;
end
if
;
end
if
;
end
process
p_rst_fr_reg
;
end
process
;
--============================================================================
-- Output enable logic
--============================================================================
fpga_oe_o
<=
'1'
;
fpga_blo_oe_o
<=
'1'
;
fpga_trig_ttl_oe_o
<=
'1'
;
fpga_inv_oe_o
<=
'1'
;
-- Pulse input valid only after inhibit period is over
pulse_in
<=
(
pulse_ttl
or
pulse_blo
)
when
(
inhibit_first_pulse_d0
=
'0'
)
else
(
others
=>
'0'
);
--============================================================================
-- TTL and blocking pulse generation logic
--============================================================================
-- First, the TTL trigger mux, selected via the TTL switch; ttlbar_nosig_n is
-- controlled in the process below
trig_ttl_a
<=
not
fpga_input_ttl_n_i
when
(
ttl_switch_n_i
=
'0'
)
else
fpga_input_ttl_n_i
and
ttlbar_nosig_n
;
-- Then, the blocking trigger
trig_blo_a
<=
fpga_blo_in_i
;
-- And now the OR gate at the inputs of the pulse generator blocks
trig_a
<=
trig_ttl_a
or
trig_blo_a
;
-----------------------------------------------------------------------------
-- Generate pulse repetition logic
-----------------------------------------------------------------------------
gen_ttl_pulse_generators
:
for
i
in
1
to
g_nr_ttl_chan
generate
-- Process to detect lack of signal on TTL line
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
-- the mux input.
p_ttlbar_nosig
:
process
(
clk20_vcxo_i
)
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
or
(
fpga_input_ttl_n_i
(
i
)
=
'0'
)
then
ttlbar_nosig_n
(
i
)
<=
'1'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
elsif
(
fpga_input_ttl_n_i
(
i
)
=
'1'
)
then
ttlbar_nosig_cnt
(
i
)
<=
ttlbar_nosig_cnt
(
i
)
+
1
;
if
(
ttlbar_nosig_cnt
(
i
)
=
1999
)
then
ttlbar_nosig_n
(
i
)
<=
'0'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
process
p_ttlbar_nosig
;
-- First, resync the trigger signal into clk20_vcxo_i domain
--
-- Reset value is '1' to keep to the post-v2.0 releases, where a pulse would
-- be counted by the pulse counter on startup, when the board is in TTL-BAR
-- repetition mode.
--
-- Due to the FPGA logic reset time of 100ms, all inputs should settle by the
-- time the reset is over, so not resetting the glitch filter is safe
cmp_sync_ffs
:
gc_sync_ffs
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_n_i
=>
'1'
,
data_i
=>
trig_a
(
i
),
synced_o
=>
trig_synced
(
i
)
);
-- Deglitch synchronized trigger signal
--
-- Reset value is '1' to keep to the post-v2.0 releases, where a pulse would
-- be counted by the pulse counter on startup, when the board is in TTL-BAR
-- repetition mode.
--
-- Due to the FPGA logic reset time of 100ms, all inputs should settle by the
-- time the reset is over, so not resetting the glitch filter is safe
cmp_inp_glitch_filt
:
gc_glitch_filt
generic
map
(
g_len
=>
c_pulse_gen_gf_len
)
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_n_i
=>
'1'
,
dat_i
=>
trig_synced
(
i
),
dat_o
=>
trig_degl
(
i
)
);
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan
(
i
)
<=
trig_a
(
i
)
when
(
extra_switch_n_i
(
1
)
=
'1'
)
else
trig_degl
(
i
);
-- Output pulse generators
cmp_ttl_pulse_gen
:
ctblo_pulse_gen
generic
map
(
g_pwidth
=>
c_pulse_gen_pwidth
,
g_duty_cycle_div
=>
c_pulse_gen_duty_cycle_div
)
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_n_i
=>
rst_n
,
en_i
=>
'1'
,
gf_en_n_i
=>
extra_switch_n_i
(
1
),
trig_a_i
=>
trig_chan
(
i
),
pulse_o
=>
pulse_outp
(
i
)
);
-- Pulse outputs assignment
fpga_out_ttl_o
<=
pulse_outp
when
(
ttl_switch_n_i
=
'0'
)
else
not
pulse_outp
;
fpga_trig_blo_o
<=
pulse_outp
;
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led
:
process
(
clk20_vcxo_i
,
rst_n
)
is
begin
if
rising_edge
(
clk20_vcxo_i
)
then
if
(
rst_n
=
'0'
)
then
pulse_outp_d0
(
i
)
<=
'0'
;
pulse_outp_r_edge_p
(
i
)
<=
'0'
;
pulse_led_cnt
(
i
)
<=
(
others
=>
'0'
);
pulse_leds
(
i
)
<=
'0'
;
else
pulse_outp_d0
(
i
)
<=
pulse_outp
(
i
);
pulse_outp_r_edge_p
(
i
)
<=
pulse_outp
(
i
)
and
(
not
pulse_outp_d0
(
i
));
case
pulse_leds
(
i
)
is
when
'0'
=>
if
(
pulse_outp_r_edge_p
(
i
)
=
'1'
)
then
pulse_leds
(
i
)
<=
'1'
;
end
if
;
when
'1'
=>
pulse_led_cnt
(
i
)
<=
pulse_led_cnt
(
i
)
+
1
;
if
(
pulse_led_cnt
(
i
)
=
(
pulse_led_cnt
(
i
)
'range
=>
'1'
))
then
pulse_leds
(
i
)
<=
'0'
;
end
if
;
when
others
=>
pulse_leds
(
i
)
<=
'0'
;
end
case
;
end
if
;
end
if
;
end
process
;
end
generate
gen_ttl_pulse_generators
;
-----------------------------------------------------------------------------
-- Line inputs for reflection in status register
line_ttl
<=
not
ttl_n_i
;
line_invttl
<=
not
inv_n_i
;
line_blo
<=
blo_i
;
-- Pulse status LED output assignments
pulse_front_led_n_o
<=
not
pulse_leds
;
pulse_rear_led_n_o
<=
not
pulse_leds
;
-- Switch inputs for reflection in status register
sw_gp
<=
not
sw_gp_n_i
;
--============================================================================
--
General-purpose INV TTL output
s
--
Instantiate common generic gateware for converter board
s
--============================================================================
inv_out_o
<=
inv_in_n_i
;
cmp_conv_common
:
conv_common_gw
generic
map
(
-- Number of repeater channels
g_nr_chans
=>
c_nr_chans
,
g_board_id
=>
c_board_id
,
g_gwvers
=>
c_gwvers
,
g_pgen_fixed_width
=>
true
,
g_pgen_pwidth
=>
24
,
g_pgen_duty_cycle_div
=>
200
,
g_pgen_gf_len
=>
1
,
g_bicolor_led_columns
=>
c_bicolor_led_cols
,
g_bicolor_led_lines
=>
c_bicolor_led_lines
)
port
map
(
-- Clocks
clk_20_i
=>
clk_20_i
,
clk_125_p_i
=>
clk_125_p_i
,
clk_125_n_i
=>
clk_125_n_i
,
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o
=>
rst_20_n
,
-- Glitch filter active-low enable signal
gf_en_n_i
=>
sw_gp_n_i
(
0
),
-- Channel enable
global_ch_oen_o
=>
global_oen_o
,
pulse_front_oen_o
=>
ttl_oen_o
,
pulse_rear_oen_o
=>
blo_oen_o
,
inv_oen_o
=>
inv_oen_o
,
-- Front panel channels
pulse_i
=>
pulse_in
,
pulse_o
=>
pulse_out
,
-- Channel leds
led_pulse_o
=>
led_pulse
,
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o
=>
led_i2c
,
-- I2C interface
scl_i
=>
scl_i
,
scl_o
=>
scl_o
,
scl_en_o
=>
scl_en_o
,
sda_i
=>
sda_i
,
sda_o
=>
sda_o
,
sda_en_o
=>
sda_en_o
,
-- VME interface
vme_sysreset_n_i
=>
vme_sysreset_n_i
,
vme_ga_i
=>
vme_ga_i
,
vme_gap_i
=>
vme_gap_i
,
-- SPI interface to on-board flash chip
flash_cs_n_o
=>
flash_cs_n_o
,
flash_sclk_o
=>
flash_sclk_o
,
flash_mosi_o
=>
flash_mosi_o
,
flash_miso_i
=>
flash_miso_i
,
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o
=>
dac20_din_o
,
dac20_sclk_o
=>
dac20_sclk_o
,
dac20_sync_n_o
=>
dac20_sync_n_o
,
-- 125 MHz clock generator control
dac125_din_o
=>
dac125_din_o
,
dac125_sclk_o
=>
dac125_sclk_o
,
dac125_sync_n_o
=>
dac125_sync_n_o
,
-- SFP lines
sfp_los_i
=>
sfp_los_i
,
sfp_mod_def0_i
=>
sfp_mod_def0_i
,
sfp_rate_select_o
=>
sfp_rate_select_o
,
sfp_mod_def1_b
=>
sfp_mod_def1_b
,
sfp_mod_def2_b
=>
sfp_mod_def2_b
,
sfp_tx_disable_o
=>
sfp_tx_disable_o
,
sfp_tx_fault_i
=>
sfp_tx_fault_i
,
-- Switch inputs (for readout from converter status register)
sw_gp_i
=>
sw_gp
,
sw_other_i
=>
(
others
=>
'0'
),
-- RTM lines
rtmm_i
=>
rtmm_i
,
rtmp_i
=>
rtmp_i
,
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i
=>
line_ttl
,
line_inv_i
=>
line_invttl
,
line_rear_i
=>
line_blo
,
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i
=>
ttlbar_nosig
,
line_inv_fs_i
=>
(
others
=>
'0'
),
line_rear_fs_i
=>
(
others
=>
'0'
),
-- Thermometer line
thermometer_b
=>
thermometer_b
,
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o
=>
led_syserr
,
-- Bicolor LED signals
bicolor_led_state_i
=>
bicolor_led_state
,
bicolor_led_col_o
=>
bicolor_led_col
,
bicolor_led_line_o
=>
bicolor_led_line
,
bicolor_led_line_oen_o
=>
bicolor_led_line_oen
);
--============================================================================
--
MultiBoo
t logic
--
Channel outpu
t logic
--============================================================================
cmp_multiboot
:
wb_xil_multiboot
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_n_i
=>
rst_n
,
-- TTL and RS-485 outputs
ttl_o
<=
pulse_out
when
sw_ttl
=
'1'
else
not
pulse_out
;
blo_o
<=
pulse_out
;
wbs_i
=>
xbar_master_out
(
c_slv_multiboot
),
wbs_o
=>
xbar_master_in
(
c_slv_multiboot
),
-- LED outputs
led_front_n_o
<=
not
led_pulse
;
led_rear_n_o
<=
not
led_pulse
;
spi_cs_n_o
=>
fpga_prom_cso_b_n_o
,
spi_sclk_o
=>
fpga_prom_cclk_o
,
spi_mosi_o
=>
fpga_prom_mosi_o
,
spi_miso_i
=>
fpga_prom_miso_i
);
-- INV-TTL outputs
inv_o
<=
inv_n_i
;
--============================================================================
-- Manual reset for blocking power supply
--============================================================================
mr_n_o
<=
rst_20_n
;
--============================================================================
--
Bicolor LED matrix logic
--
External logic for bicolor LED control
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- Assign bicolor LED lines & columns to outputs
led_wr_ownaddr_i2c_o
<=
bicolor_led_col
(
0
);
led_wr_gmt_ttl_ttln_o
<=
bicolor_led_col
(
1
);
led_wr_link_syserror_o
<=
bicolor_led_col
(
2
);
led_wr_ok_syspw_o
<=
bicolor_led_col
(
3
);
led_multicast_2_0_o
<=
bicolor_led_col
(
4
);
led_multicast_3_1_o
<=
bicolor_led_col
(
5
);
led_ctrl0_o
<=
bicolor_led_line
(
0
);
led_ctrl1_o
<=
bicolor_led_line
(
1
);
led_ctrl0_oen_o
<=
bicolor_led_line_oen
(
0
);
led_ctrl1_oen_o
<=
bicolor_led_line_oen
(
1
);
-- WR address
bicolor_led_state
(
1
downto
0
)
<=
c_LED_OFF
;
...
...
@@ -859,18 +471,17 @@ begin
-- MULTICAST 1
bicolor_led_state
(
11
downto
10
)
<=
c_LED_OFF
;
-- I2C
bicolor_led_state
(
13
downto
12
)
<=
c_LED_GREEN
when
(
led_i2c
=
'1'
)
else
c_LED_RED
when
(
led_i2c_err
=
'1'
)
else
c_LED_OFF
;
-- State of TTL/TTL_N switch
bicolor_led_state
(
15
downto
14
)
<=
c_LED_GREEN
when
(
ttl_switch_n_i
=
'0
'
)
else
bicolor_led_state
(
15
downto
14
)
<=
c_LED_GREEN
when
(
sw_ttl
=
'1
'
)
else
c_LED_OFF
;
-- System error
bicolor_led_state
(
17
downto
16
)
<=
c_LED_RED
when
(
rtmm_ok
=
'0'
)
and
(
rtmp_ok
=
'0'
)
else
bicolor_led_state
(
17
downto
16
)
<=
c_LED_RED
when
(
led_syserr
=
'1'
)
or
(
c_gwvers
(
7
downto
4
)
=
"0000"
)
else
c_LED_OFF
;
-- System power
...
...
@@ -882,68 +493,7 @@ begin
-- MULTICAST 3
bicolor_led_state
(
23
downto
22
)
<=
c_LED_OFF
;
cmp_bicolor_led_ctrl
:
bicolor_led_ctrl
generic
map
(
g_NB_COLUMN
=>
6
,
g_NB_LINE
=>
2
,
g_clk_freq
=>
20000000
,
g_refresh_rate
=>
250
)
port
map
(
clk_i
=>
clk20_vcxo_i
,
rst_n_i
=>
rst_n
,
led_intensity_i
=>
"1111111"
,
led_state_i
=>
bicolor_led_state
,
column_o
(
0
)
=>
led_wr_ownaddr_i2c_o
,
column_o
(
1
)
=>
led_wr_gmt_ttl_ttln_o
,
column_o
(
2
)
=>
led_wr_link_syserror_o
,
column_o
(
3
)
=>
led_wr_ok_syspw_o
,
column_o
(
4
)
=>
led_multicast_2_0_o
,
column_o
(
5
)
=>
led_multicast_3_1_o
,
line_o
(
0
)
=>
led_ctrl0_o
,
line_o
(
1
)
=>
led_ctrl1_o
,
line_oen_o
(
0
)
=>
led_ctrl0_oen_o
,
line_oen_o
(
1
)
=>
led_ctrl1_oen_o
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm
<=
not
fpga_rtmm_n_i
;
rtmp
<=
not
fpga_rtmp_n_i
;
cmp_rtm_detector
:
rtm_detector
port
map
(
rtmm_i
=>
rtmm
,
rtmp_i
=>
rtmp
,
rtmm_ok_o
=>
rtmm_ok
,
rtmp_ok_o
=>
rtmp_ok
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- Theremometer output to high-impedance
thermometer_b
<=
'Z'
;
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o
<=
'1'
;
fpga_plldac1_din_o
<=
'0'
;
fpga_plldac1_sclk_o
<=
'0'
;
fpga_plldac2_sync_n_o
<=
'1'
;
fpga_plldac2_din_o
<=
'0'
;
fpga_plldac2_sclk_o
<=
'0'
;
-- SFP lines all open-drain, set to high-impedance
fpga_sfp_rate_select_o
<=
'Z'
;
fpga_sfp_mod_def1_b
<=
'Z'
;
fpga_sfp_mod_def2_b
<=
'Z'
;
fpga_sfp_tx_disable_o
<=
'Z'
;
end
behav
;
end
architecture
arch
;
--==============================================================================
-- architecture end
--==============================================================================
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