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Conv TTL Blocking - Gateware
Commit cc71e6a0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Rename conv_pulse_gen to ctblo_pulse_gen 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 0dd7106c
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Showing with 9 additions and 9 deletions
modules/Release/Manifest.py
View file @ cc71e6a0
files = [ files = [
"conv_regs.vhd", "conv_regs.vhd",
"conv_pulse_gen.vhd", "ctblo_pulse_gen.vhd",
"conv_man_trig.vhd", "conv_man_trig.vhd",
"conv_ring_buf.vhd", "conv_ring_buf.vhd",
"conv_pulse_timetag.vhd" "conv_pulse_timetag.vhd"
......
modules/Release/conv_pulse_timetag.vhd
View file @ cc71e6a0
...@@ -76,7 +76,7 @@ entity conv_pulse_timetag is ...@@ -76,7 +76,7 @@ entity conv_pulse_timetag is
chan_o : out std_logic_vector(g_nr_chan downto 1); chan_o : out std_logic_vector(g_nr_chan downto 1);
-- Ring buffer I/O -- Ring buffer I/O
buf_wr_req_p_o : out std_logic buf_wr_req_p_o : out std_logic
); );
end entity conv_pulse_timetag; end entity conv_pulse_timetag;
......
modules/Release/conv_pulse_gen.vhd → modules/Release/ctblo_pulse_gen.vhd
View file @ cc71e6a0
...@@ -57,7 +57,7 @@ library ieee; ...@@ -57,7 +57,7 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
entity conv_pulse_gen is entity ctblo_pulse_gen is
generic generic
( (
-- Pulse width, in number of clk_i cycles -- Pulse width, in number of clk_i cycles
...@@ -93,10 +93,10 @@ entity conv_pulse_gen is ...@@ -93,10 +93,10 @@ entity conv_pulse_gen is
-- glitch filter enabled: glitch filter length + 5 clk_i cycles -- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic pulse_o : out std_logic
); );
end entity conv_pulse_gen; end entity ctblo_pulse_gen;
architecture behav of conv_pulse_gen is architecture behav of ctblo_pulse_gen is
--============================================================================ --============================================================================
-- Type declarations -- Type declarations
......
syn/Release/conv_ttl_blo.xise
View file @ cc71e6a0
...@@ -347,7 +347,7 @@ ...@@ -347,7 +347,7 @@
<file xil_pn:name="../../modules/Release/conv_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/Release/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="../../modules/Release/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/Release/ctblo_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
......
top/Release/conv_ttl_blo.vhd
View file @ cc71e6a0
...@@ -284,7 +284,7 @@ architecture behav of conv_ttl_blo is ...@@ -284,7 +284,7 @@ architecture behav of conv_ttl_blo is
-- Pulse generator component -- Pulse generator component
-- (use: output pulse generation, pulse status LEDs) -- (use: output pulse generation, pulse status LEDs)
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component conv_pulse_gen is component ctblo_pulse_gen is
generic generic
( (
-- Pulse width, in number of clk_i cycles -- Pulse width, in number of clk_i cycles
...@@ -320,7 +320,7 @@ architecture behav of conv_ttl_blo is ...@@ -320,7 +320,7 @@ architecture behav of conv_ttl_blo is
-- glitch filter enabled: glitch filter length + 5 clk_i cycles -- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic pulse_o : out std_logic
); );
end component conv_pulse_gen; end component ctblo_pulse_gen;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- RTM detector component -- RTM detector component
...@@ -1214,7 +1214,7 @@ begin ...@@ -1214,7 +1214,7 @@ begin
pgen_trig(i) <= trig_chan(i) or trig_man(i); pgen_trig(i) <= trig_chan(i) or trig_man(i);
-- Output pulse generators -- Output pulse generators
cmp_pulse_gen : conv_pulse_gen cmp_pulse_gen : ctblo_pulse_gen
generic map generic map
( (
g_pwidth => c_pulse_gen_pwidth, g_pwidth => c_pulse_gen_pwidth,
......
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