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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
cc71e6a0
Commit
cc71e6a0
authored
Mar 26, 2014
by
Theodor-Adrian Stana
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Rename conv_pulse_gen to ctblo_pulse_gen
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
0dd7106c
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5 changed files
with
9 additions
and
9 deletions
+9
-9
Manifest.py
modules/Release/Manifest.py
+1
-1
conv_pulse_timetag.vhd
modules/Release/conv_pulse_timetag.vhd
+1
-1
ctblo_pulse_gen.vhd
modules/Release/ctblo_pulse_gen.vhd
+3
-3
conv_ttl_blo.xise
syn/Release/conv_ttl_blo.xise
+1
-1
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+3
-3
No files found.
modules/Release/Manifest.py
View file @
cc71e6a0
files
=
[
"conv_regs.vhd"
,
"c
onv
_pulse_gen.vhd"
,
"c
tblo
_pulse_gen.vhd"
,
"conv_man_trig.vhd"
,
"conv_ring_buf.vhd"
,
"conv_pulse_timetag.vhd"
...
...
modules/Release/conv_pulse_timetag.vhd
View file @
cc71e6a0
...
...
@@ -76,7 +76,7 @@ entity conv_pulse_timetag is
chan_o
:
out
std_logic_vector
(
g_nr_chan
downto
1
);
-- Ring buffer I/O
buf_wr_req_p_o
:
out
std_logic
buf_wr_req_p_o
:
out
std_logic
);
end
entity
conv_pulse_timetag
;
...
...
modules/Release/c
onv
_pulse_gen.vhd
→
modules/Release/c
tblo
_pulse_gen.vhd
View file @
cc71e6a0
...
...
@@ -57,7 +57,7 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
c
onv
_pulse_gen
is
entity
c
tblo
_pulse_gen
is
generic
(
-- Pulse width, in number of clk_i cycles
...
...
@@ -93,10 +93,10 @@ entity conv_pulse_gen is
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o
:
out
std_logic
);
end
entity
c
onv
_pulse_gen
;
end
entity
c
tblo
_pulse_gen
;
architecture
behav
of
c
onv
_pulse_gen
is
architecture
behav
of
c
tblo
_pulse_gen
is
--============================================================================
-- Type declarations
...
...
syn/Release/conv_ttl_blo.xise
View file @
cc71e6a0
...
...
@@ -347,7 +347,7 @@
<file
xil_pn:name=
"../../modules/Release/conv_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3"
/>
</file>
<file
xil_pn:name=
"../../modules/Release/c
onv
_pulse_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../modules/Release/c
tblo
_pulse_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
top/Release/conv_ttl_blo.vhd
View file @
cc71e6a0
...
...
@@ -284,7 +284,7 @@ architecture behav of conv_ttl_blo is
-- Pulse generator component
-- (use: output pulse generation, pulse status LEDs)
------------------------------------------------------------------------------
component
c
onv
_pulse_gen
is
component
c
tblo
_pulse_gen
is
generic
(
-- Pulse width, in number of clk_i cycles
...
...
@@ -320,7 +320,7 @@ architecture behav of conv_ttl_blo is
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o
:
out
std_logic
);
end
component
c
onv
_pulse_gen
;
end
component
c
tblo
_pulse_gen
;
------------------------------------------------------------------------------
-- RTM detector component
...
...
@@ -1214,7 +1214,7 @@ begin
pgen_trig
(
i
)
<=
trig_chan
(
i
)
or
trig_man
(
i
);
-- Output pulse generators
cmp_pulse_gen
:
c
onv
_pulse_gen
cmp_pulse_gen
:
c
tblo
_pulse_gen
generic
map
(
g_pwidth
=>
c_pulse_gen_pwidth
,
...
...
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