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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
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ca1e666a
Commit
ca1e666a
authored
Jan 07, 2014
by
Theodor-Adrian Stana
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Compiled pulsetest firmware
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
68e5ac71
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pulsetest.xise
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syn/pulsetest/pulsetest.xise
View file @
ca1e666a
...
...
@@ -175,7 +175,7 @@
<property
xil_pn:name=
"Optimization Effort spartan6"
xil_pn:value=
"Normal"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"Speed"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
"
"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
"
-g next_config_register_write:Disable"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Par"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
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