Commit c74ddcd8 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

hdl: Made manual pulse trigger work properly

Prior to this commit, manual pulse triggering did not work when the glitch
filter was enabled. Now, this was fixed by extending the trigger pulse the
conv_man_trig module generates. This accounts for the situation where the
pulse generator has the glitch filter enabled.

I also fixed a bug in conv_pulse_gen; this fix was commited two commits ago.
The bug consisted of the gf_off part of the pulse generator triggering even
when the glitch filter was enabled. This resulted in a continuous high pulse
generated on the output when the glitch filter was switched from on to off.
Granted, such a situation should not occur in operation, since a board needs
to be removed from the crate in order to flip a switch. Nonetheless, it was a
but, so I've fixed it by making sure the gf_off part of the design only triggers
when the glitch filter is disabled:

if (en_i = '1') and (gf_en_n_i = '1') then
  pulse_gf_off <= '1';
end if;

A warning will be placed in the docs for release versions 1.0 and 0.0 (golden).
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 80e35812
......@@ -10,12 +10,38 @@
-- version: 1.0
--
-- description:
-- This module generates a pulse for the conv_pulse_gen module for manually
-- triggering a debug pulse on a channel output. It works in conjunction
-- with the converter board registers component (conv_regs), from where it
-- obtains the value of the MPT (manual pulse trigger) field in the control
-- register.
--
-- To manually trigger a pulse, a magic sequence of numbers (0xde, 0xad, 0xbe,
-- 0xef) should first be sent to the MPT field, followed by the channel number
-- to send the pulse on. When the channel number is sent, a single pulse is
-- generated by the conv_pulse_gen component at the output.
--
-- The conv_man_trig module checks to see whether the proper magic sequence
-- is written the the MPT field using a simple FSM. The FSM advances when
-- the MPT field is written, if the MPT field corresponds to the proper byte
-- in the magic sequence. If at any time during the magic sequence the value
-- of the MPT field does not correspond to the expected value, the FSM returns
-- to IDLE.
--
-- After the magic sequence is received, the FSM waits for the channel number
-- to be written to the MPT. If a valid channel number is input, a pulse is
-- generated on this channel. The check of whether a valid number is input is
-- based on the g_nr_ttl_chan generic. Should an invalid channel number be
-- input, no error is reported and no pulse is generated.
--
-- The output trigger pulse is extended within the last state of the FSM, to
-- account for when the glitch filter of the conv_pulse_gen component is on.
-- To extend the pulse by an appropriate number of clock cycles, the length
-- of the conv_pulse_gen glitch filter should be input via the g_gf_len.
--
-- dependencies:
-- genram_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
......@@ -45,7 +71,11 @@ entity conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6
g_nr_chan : positive := 6;
-- Length of pulse generator glitch filter, needed to generate a long
-- enough pulse
g_gf_len : positive := 1
);
port
(
......@@ -58,7 +88,7 @@ entity conv_man_trig is
reg_i : in std_logic_vector(7 downto 0);
-- One-clock pulse output
p_o : out std_logic_vector(g_nr_chan downto 1)
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end entity conv_man_trig;
......@@ -78,6 +108,7 @@ architecture behav of conv_man_trig is
PASS1,
PASS2,
PASS3,
GET_CHAN,
GEN
);
......@@ -115,6 +146,7 @@ architecture behav of conv_man_trig is
-- "Password" and channel number signals
signal pass : std_logic_vector(7 downto 0);
signal chnr : std_logic_vector(f_log2_size(g_nr_chan)-1 downto 0);
signal cnt : unsigned(f_log2_size(g_gf_len)-1 downto 0);
--==============================================================================
-- architecture begin
......@@ -133,22 +165,33 @@ begin
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
p_o <= (others => '0');
state <= IDLE;
cnt <= (others => '0');
trig_o <= (others => '0');
else
case state is
when IDLE =>
p_o <= (others => '0');
trig_o <= (others => '0');
f_change_state(reg_ld_i, pass, 0, state, PASS1);
when PASS1 =>
f_change_state(reg_ld_i, pass, 1, state, PASS2);
when PASS2 =>
f_change_state(reg_ld_i, pass, 2, state, PASS3);
when PASS3 =>
f_change_state(reg_ld_i, pass, 3, state, GEN);
when GEN =>
f_change_state(reg_ld_i, pass, 3, state, GET_CHAN);
when GET_CHAN =>
if (reg_ld_i = '1') then
p_o(to_integer(unsigned(chnr))) <= '1';
for i in 1 to g_nr_chan loop
if i = to_integer(unsigned(chnr)) then
trig_o(i) <= '1';
end if;
end loop;
cnt <= (others => '0');
state <= GEN;
end if;
when GEN =>
cnt <= cnt + 1;
if (cnt = g_gf_len-1) then
state <= IDLE;
end if;
when others =>
......
......@@ -39,8 +39,8 @@ CWD := $(shell pwd)
FILES := ../../top/Release/conv_ttl_blo.ucf \
../../top/Release/conv_ttl_blo.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/Release/conv_pulse_gen.vhd \
../../modules/Release/conv_man_trig.vhd \
../../modules/conv_pulse_gen.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
......
......@@ -347,10 +347,10 @@
<file xil_pn:name="../../modules/Release/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../modules/Release/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/Release/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/Release/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../modules/reset_gen.vhd" xil_pn:type="FILE_VHDL">
......
......@@ -181,14 +181,14 @@ architecture behav of conv_ttl_blo is
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 2;
-----------------------------------------
------------------------------------------------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
------------------------------------------------------------------------------
-- CONV_REGS [000-040]
-- MULTIBOOT [040-080]
-----------------------------------------
------------------------------------------------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
......@@ -215,11 +215,18 @@ architecture behav of conv_ttl_blo is
c_slv_multiboot => c_mask_multiboot
);
------------------------------------------------------------------------------
-- Pulse generator glitch filter length
------------------------------------------------------------------------------
constant c_pulse_gen_gf_len : positive := 1;
--============================================================================
-- Component declarations
--============================================================================
------------------------------------------------------------------------------
-- Reset generator component
-- (use: global reset generation, output reset generation)
------------------------------------------------------------------------------
component reset_gen is
generic
(
......@@ -234,8 +241,10 @@ architecture behav of conv_ttl_blo is
);
end component reset_gen;
------------------------------------------------------------------------------
-- Pulse generator component
-- (use: output pulse generation, pulse status LEDs)
------------------------------------------------------------------------------
component conv_pulse_gen is
generic
(
......@@ -277,8 +286,10 @@ architecture behav of conv_ttl_blo is
);
end component conv_pulse_gen;
------------------------------------------------------------------------------
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
------------------------------------------------------------------------------
component rtm_detector is
port
(
......@@ -289,7 +300,9 @@ architecture behav of conv_ttl_blo is
);
end component rtm_detector;
------------------------------------------------------------------------------
-- Converter board control registers
------------------------------------------------------------------------------
component conv_regs is
port (
rst_n_i : in std_logic;
......@@ -353,8 +366,10 @@ architecture behav of conv_ttl_blo is
);
end component conv_regs;
------------------------------------------------------------------------------
-- MultiBoot component
-- use: remotely reprogram the FPGA
------------------------------------------------------------------------------
component wb_xil_multiboot is
port
(
......@@ -374,27 +389,34 @@ architecture behav of conv_ttl_blo is
);
end component wb_xil_multiboot;
------------------------------------------------------------------------------
-- Manual pulse trigger component
------------------------------------------------------------------------------
component conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6
g_nr_chan : positive := 6;
-- Length of pulse generator glitch filter, needed to generate a long
-- enough pulse
g_gf_len : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- One-clock pulse output
p_o : out std_logic_vector(g_nr_chan downto 1)
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end component conv_man_trig;
------------------------------------------------------------------------------
--============================================================================
-- Signal declarations
......@@ -764,7 +786,8 @@ begin
cmp_man_trig : conv_man_trig
generic map
(
g_nr_chan => g_nr_ttl_chan
g_nr_chan => g_nr_ttl_chan,
g_gf_len => c_pulse_gen_gf_len
)
port map
(
......@@ -777,7 +800,7 @@ begin
reg_i => mpt,
-- One-clock pulse output
p_o => trig_man
trig_o => trig_man
);
-- And now the OR gate at the inputs of the pulse generator blocks
......@@ -838,7 +861,7 @@ begin
generic map
(
g_pwidth => 24,
g_gf_len => 1
g_gf_len => c_pulse_gen_gf_len
)
port map
(
......
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