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Conv TTL Blocking - Gateware
Commit bac8cfc2 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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new approach, software writes to flash directly

parent 653b8796
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Showing with 1860 additions and 940 deletions
hdl/multiboot/rtl/m25p_flash-with-write.vhd 0 → 100644
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hdl/multiboot/rtl/m25p_flash.vhd
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hdl/multiboot/rtl/multiboot_fsm.vhd
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hdl/multiboot/rtl/multiboot_regs.vhd
View file @ bac8cfc2
......@@ -57,22 +57,30 @@ entity multiboot_regs is
multiboot_cr_wmb_o : out std_logic;
multiboot_cr_wgb_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
multiboot_cr_flr_o : out std_logic;
multiboot_cr_flw_o : out std_logic;
--multiboot_cr_flr_o : out std_logic;
--multiboot_cr_flw_o : out std_logic;
-- Fields of status register
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
multiboot_sr_flrrdy_i : in std_logic;
multiboot_sr_flwrdy_i : in std_logic;
--multiboot_sr_flrrdy_i : in std_logic;
--multiboot_sr_flwrdy_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
-- Fields of bitstream address registers
multiboot_flrdr_i : in std_logic_vector(31 downto 0);
multiboot_flwdr_o : out std_logic_vector(31 downto 0)
-- Fields of FAR register
multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(7 downto 0);
multiboot_far_data_o : out std_logic_vector(7 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_ready_i : in std_logic;
multiboot_far_cs_o : out std_logic
---- Fields of bitstream address registers
--multiboot_flrdr_i : in std_logic_vector(31 downto 0);
--multiboot_flwdr_o : out std_logic_vector(31 downto 0)
);
end multiboot_regs;
......@@ -92,6 +100,10 @@ signal multiboot_gbbar_int : std_logic_vector(31 downto 0);
signal multiboot_mbbar_int : std_logic_vector(31 downto 0);
signal multiboot_flrdr_int : std_logic_vector(31 downto 0);
signal multiboot_flwdr_int : std_logic_vector(31 downto 0);
signal multiboot_far_data_load_int : std_logic;
signal multiboot_far_xfer_int : std_logic;
signal multiboot_far_ready_int : std_logic;
signal multiboot_far_cs_int : std_logic;
signal ack_sreg : std_logic_vector(1 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -106,35 +118,41 @@ begin
multiboot_sr_bootsts_img_int <= multiboot_sr_bootsts_img_i;
multiboot_sr_valid_int <= multiboot_sr_valid_i;
multiboot_sr_flrrdy_int <= multiboot_sr_flrrdy_i;
multiboot_sr_flwrdy_int <= multiboot_sr_flwrdy_i;
multiboot_flrdr_int <= multiboot_flrdr_i;
--multiboot_sr_flrrdy_int <= multiboot_sr_flrrdy_i;
--multiboot_sr_flwrdy_int <= multiboot_sr_flwrdy_i;
--multiboot_flrdr_int <= multiboot_flrdr_i;
multiboot_far_ready_int <= multiboot_far_ready_i;
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= (others => '0');
ack_in_progress <= '0';
rddata_reg <= (others => '0');
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_cr_flr_int <= '0';
multiboot_gbbar_int <= (others => '0');
multiboot_mbbar_int <= (others => '0');
ack_sreg <= (others => '0');
ack_in_progress <= '0';
rddata_reg <= (others => '0');
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
--multiboot_cr_flr_int <= '0';
multiboot_gbbar_int <= (others => '0');
multiboot_mbbar_int <= (others => '0');
multiboot_far_data_load_int <= '0';
multiboot_far_xfer_int <= '0';
multiboot_far_cs_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(0) <= ack_sreg(1);
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_cr_flr_int <= '0';
multiboot_cr_flw_int <= '0';
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_far_data_load_int <= '0';
--multiboot_cr_flr_int <= '0';
--multiboot_cr_flw_int <= '0';
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
......@@ -148,15 +166,17 @@ begin
multiboot_cr_wmb_int <= wrdata_reg(1);
multiboot_cr_wgb_int <= wrdata_reg(2);
multiboot_cr_iprog_int <= wrdata_reg(3);
multiboot_cr_flr_int <= wrdata_reg(4);
multiboot_cr_flw_int <= wrdata_reg(5);
--multiboot_cr_flr_int <= wrdata_reg(4);
--multiboot_cr_flw_int <= wrdata_reg(5);
end if;
rddata_reg(0) <= multiboot_cr_rdbootsts_int;
rddata_reg(1) <= multiboot_cr_wmb_int;
rddata_reg(2) <= multiboot_cr_wgb_int;
rddata_reg(3) <= multiboot_cr_iprog_int;
rddata_reg(4) <= multiboot_cr_flr_int;
rddata_reg(5) <= multiboot_cr_flw_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
--rddata_reg(4) <= multiboot_cr_flr_int;
--rddata_reg(5) <= multiboot_cr_flw_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -190,8 +210,8 @@ begin
end if;
rddata_reg(15 downto 0) <= multiboot_sr_bootsts_img_int;
rddata_reg(16) <= multiboot_sr_valid_int;
rddata_reg(17) <= multiboot_sr_flrrdy_int;
rddata_reg(18) <= multiboot_sr_flwrdy_int;
rddata_reg(17) <= 'X'; --multiboot_sr_flrrdy_int;
rddata_reg(18) <= 'X'; --multiboot_sr_flwrdy_int;
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
......@@ -222,16 +242,24 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
rddata_reg <= multiboot_flrdr_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
multiboot_flwdr_int <= wrdata_reg;
multiboot_far_data_load_int <= '1';
multiboot_far_xfer_int <= wrdata_reg(8);
multiboot_far_cs_int <= wrdata_reg(10);
end if;
rddata_reg <= multiboot_flwdr_int;
rddata_reg(7 downto 0) <= multiboot_far_data_i;
rddata_reg(8) <= multiboot_far_xfer_int;
rddata_reg(9) <= multiboot_far_ready_int;
rddata_reg(10) <= multiboot_far_cs_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
-- when "101" =>
-- if (wb_we_i = '1') then
-- multiboot_flwdr_int <= wrdata_reg;
-- end if;
-- rddata_reg <= multiboot_flwdr_int;
-- ack_sreg(0) <= '1';
-- ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -255,16 +283,21 @@ begin
multiboot_cr_wgb_o <= multiboot_cr_wgb_int;
-- IPROG
multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
-- Flash read
multiboot_cr_flr_o <= multiboot_cr_flr_int;
-- Flash write
multiboot_cr_flw_o <= multiboot_cr_flw_int;
---- Flash read
-- multiboot_cr_flr_o <= multiboot_cr_flr_int;
---- Flash write
-- multiboot_cr_flw_o <= multiboot_cr_flw_int;
-- GBBAR
multiboot_gbbar_o <= multiboot_gbbar_int;
-- MBBAR
multiboot_mbbar_o <= multiboot_mbbar_int;
-- Flash data word
multiboot_flwdr_o <= multiboot_flwdr_int;
-- FAR outputs
multiboot_far_data_o <= wrdata_reg(7 downto 0);
multiboot_far_data_load_o <= multiboot_far_data_load_int;
multiboot_far_xfer_o <= multiboot_far_xfer_int;
multiboot_far_cs_o <= multiboot_far_cs_int;
---- Flash data word
-- multiboot_flwdr_o <= multiboot_flwdr_int;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
hdl/multiboot/rtl/xil_multiboot.vhd
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hdl/multiboot/sim/dump.txt
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hdl/multiboot/sim/run.do
View file @ bac8cfc2
......@@ -22,4 +22,4 @@ vsim -voptargs="+acc" -lib work work.testbench
# add wave *
do wave.do
run 2.5 ms
run 0.7 sec
hdl/multiboot/sim/testbench.vhd
View file @ bac8cfc2
......@@ -116,8 +116,8 @@ architecture behav of testbench is
tRES2: TIME := 30 us; --
tW: TIME := 15 ms; -- write status register cycle time
tPP: TIME := 0.64 ms; -- page program cycle time
tSE: TIME := 3 sec; -- sector erase cycle time
tBE: TIME := 80 sec; -- bulk erase cycle time
tSE: TIME := 0.6 sec; -- sector erase cycle time
tBE: TIME := 13 sec; -- bulk erase cycle time
tVSL: TIME := 30 us; -- Vcc(min) to /S low
tPUW: TIME := 1 ms; -- Time delay to write instruction
Vwi: REAL := 2.5 ; -- Write inhibit voltage (unit: V)
......@@ -243,7 +243,7 @@ begin
-- Write flash address
wait for 200 ns;
str <= "wr-faddr";
str <= "fl addr ";
adr <= x"00000008";
dat <= x"00000010";
write <= '1';
......@@ -253,7 +253,7 @@ begin
-- Init flash read
wait for 200 ns;
str <= "wr-rdf ";
str <= "read fl ";
adr <= x"00000000";
dat <= x"00000010";
write <= '1';
......@@ -265,7 +265,7 @@ begin
-- Write flash data
wait for 200 ns;
str <= "wr-fdata";
str <= "erase ";
adr <= x"00000014";
dat <= x"12344321";
write <= '1';
......@@ -273,9 +273,9 @@ begin
wait for c_clk_per;
transfer <= '0';
-- Init flash write
-- Init flash erase
wait for 200 ns;
str <= "wr-start";
str <= "st erase";
adr <= x"00000000";
dat <= x"00000020";
write <= '1';
......@@ -283,7 +283,17 @@ begin
wait for c_clk_per;
transfer <= '0';
wait for 1 ms;
wait for 605 ms;
-- Init flash write
wait for 200 ns;
str <= "st write";
adr <= x"00000000";
dat <= x"00000020";
write <= '1';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- Init flash read
wait for 200 ns;
......
hdl/multiboot/sim/transcript
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hdl/multiboot/sim/wave.do
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hdl/multiboot/syn/conv_ttl_blo.gise
View file @ bac8cfc2
......@@ -53,7 +53,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
......@@ -64,7 +63,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
......@@ -75,35 +73,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227557" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227557" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227557" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227557" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227557" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227557" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227557" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136923" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1378136900">
<transform xil_pn:end_ts="1378227574" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1378227557">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -121,11 +119,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1378136923" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1378136923">
<transform xil_pn:end_ts="1378227574" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1378227574">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1378136933" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1378136923">
<transform xil_pn:end_ts="1378227582" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1378227574">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,7 +132,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1378137024" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1378136933">
<transform xil_pn:end_ts="1378227649" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1378227582">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -147,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1378137078" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1378137024">
<transform xil_pn:end_ts="1378227686" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1378227649">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -161,7 +159,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1378137114" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1378137078">
<transform xil_pn:end_ts="1378227708" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1378227686">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -173,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1378137078" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1378137067">
<transform xil_pn:end_ts="1378227686" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1378227675">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
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