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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
b7a79518
Commit
b7a79518
authored
Mar 06, 2014
by
Theodor-Adrian Stana
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Commit gateware v2.0
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
fb16540a
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8 changed files
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698 additions
and
483 deletions
+698
-483
pulse-gen.svg
doc/hdlguide/fig/pulse-gen.svg
+68
-8
timetag-arch.svg
doc/hdlguide/fig/timetag-arch.svg
+144
-108
timetag-core.svg
doc/hdlguide/fig/timetag-core.svg
+303
-98
hdlguide-conv-ttl-blo.tex
doc/hdlguide/hdlguide-conv-ttl-blo.tex
+47
-24
conv_pulse_gen.vhd
modules/Release/conv_pulse_gen.vhd
+20
-3
Makefile
syn/Release/Makefile
+0
-161
conv_ttl_blo.xise
syn/Release/conv_ttl_blo.xise
+14
-14
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+102
-67
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
View file @
b7a79518
...
...
@@ -527,7 +527,7 @@ the input trigger is sampled with the 20~MHz clock prior to it being input to th
(see Figure~
\ref
{
fig:hdl-bd
}
).
\begin{figure}
[h]
\
includegraphics
[width=.9\textwidth]
{
fig/pulse-gen
}
\
centerline
{
\includegraphics
[width=\textwidth]
{
fig/pulse-gen
}
}
\caption
{
Pulse generator block
}
\label
{
fig:pulse-gen
}
\end{figure}
...
...
@@ -554,9 +554,15 @@ to a pulse length which is unsafe for the controlling MOSFET on the CONV-TTL-BLO
With the glitch filter enabled, the rising edge on
\textit
{
SGF1
}
sets
\textit
{
OGF1
}
,
and this will be kept high until the counter reaches the value corresponding to the
pulse width. Note that since the external glitch filter already contains synchronization
FFs, the input trigger signal is already synchronized into the 20~MHz clock domain, and
is fed directly to the input of the FSM.
pulse width. The input trigger signal is synchronized into the 20~MHz clock domain outside
the
\textit
{
conv
\_
pulse
\_
gen
}
block, and is fed directly to the input of the FSM.
Before being fed to the FSM, however, the glitch-filtered signal is passed through a
\textit
{
pulse
inhibit circuit
}
, which inhibits the first pulse when the board is in TTL-BAR repetition mode.
In this mode, an unconnected channel is always HIGH and until the
\textit
{
no signal detect
}
block outside the
\textit
{
conv
\_
pulse
\_
gen
}
block (see the next
subsection) triggers, the continuous HIGH signal will trigger a pulse, due to the reset
state of the rising-edge detector on the FSM input.
After the pulse generation period, the FSM goes into a pulse rejection state,
where the pulse reset is kept high. If any pulses arrive on the input while the FSM
...
...
@@ -612,7 +618,7 @@ channel.
\end{figure}
Both the
\textit
{
no signal detect
}
block and the glitch filter are generated
pe
r each channel in the top-level VHDL file of the design.
fo
r each channel in the top-level VHDL file of the design.
%==============================================================================
% SEC: Pulse counters
...
...
@@ -727,10 +733,10 @@ state (Figure~\ref{fig:man-trig-fsm}).
\centerline
{
\begin{tabular}
{
l l
l
}
\begin{tabular}
{
l l
p
{
.5
\textwidth
}
}
\hline
\textbf
{
Entity
}
&
\textit
{
pulse
\_
timetag
}
&
\\
\textbf
{
Generics
}
&
\textit
{
g
\_
clk
\_
rate
}
&
Frequency in Hz of
clk
\_
i
signal
\\
\textbf
{
Generics
}
&
\textit
{
g
\_
clk
\_
rate
}
&
Frequency in Hz of
\textit
{
clk
\_
i
}
signal
\\
&
\textit
{
g
\_
nr
\_
chan
}
&
Pulse repeater number of channels
\\
\textbf
{
Ports
}
&
\textit
{
clk
\_
i
}
&
Clock signal
\\
&
\textit
{
rst
\_
n
\_
i
}
&
Active-low reset signal
\\
...
...
@@ -747,7 +753,8 @@ state (Figure~\ref{fig:man-trig-fsm}).
&
\textit
{
tm
\_
wpres
\_
o
}
&
Time from WRPC is valid
\\
&
\textit
{
chan
\_
o
}
&
Trigger channel to FIFO
\\
&
\textit
{
fifo
\_
full
\_
i
}
&
FIFO status input
\\
&
\textit
{
fifo
\_
wr
\_
req
\_
o
}
&
FIFO write request output
\\
&
\textit
{
fifo
\_
wr
\_
req
\_
o
}
&
FIFO write request output, max. four clock cycles
delay after pulse rising edge
\\
\hline
\end{tabular}
}
...
...
@@ -755,37 +762,44 @@ state (Figure~\ref{fig:man-trig-fsm}).
\vspace*
{
11pt
}
A simplified view of the time-tagging architecture is shown in Figure~
\ref
{
fig:timetag-arch
}
.
There are two clock domains in the design. The time-tag controller and the time from the
WRPC are both in the 125~MHz clock domain, while the
\textit
{
conv
\_
regs
}
component is in the
20~MHz clock domain. The FIFO is asynchronous and clocked by both the 125 and 20~MHz clocks.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=.9
7
\textwidth]
{
fig/timetag-arch
}}
\centerline
{
\includegraphics
[width=.9\textwidth]
{
fig/timetag-arch
}}
\caption
{
Time-tag architecture
}
\label
{
fig:timetag-arch
}
\end{figure}
The time-tag controller in the figure is the
\textit
{
pulse
\_
timetag
}
VHDL component.
It is designed to be connected directly to the FIFO as shown above.
In fact, as opposed to what the simplified architecture above shows, the time-tag
controller also implements the local time counters. The block's design is presented in
Figure~
\ref
{
fig:timetag-core
}
. This figure shows the functioning when the
\textit
{
pulse
\_
timetag
}
component is clocked from 125~MHz clock, as is the case in the converter board designs.
A free-running counter inside the block counts the ticks of the
\textit
{
clk
\_
i
}
signal
to count the seconds. When it reaches the value
\textit
{
g
\_
clk
\_
rate-1
}
(125~mega in
the figure), it resets and sends a "tick" to the TAI seconds counter, which then increments.
It is designed to be connected directly to the FIFO as shown above.As opposed to what the
simplified architecture above shows, the time-tag controller also implements the local time counters.
The block's design is presented in Figure~
\ref
{
fig:timetag-core
}
. This figure shows the functioning
when the
\textit
{
pulse
\_
timetag
}
component is clocked from the 125~MHz clock, as is the case in the
converter board designs. Note however that the component can work with any clock rate by changing
the
\textit
{
g
\_
clk
\_
rate
}
generic.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=\textwidth]
{
fig/timetag-core
}}
\centerline
{
\includegraphics
[width=
.9
\textwidth]
{
fig/timetag-core
}}
\caption
{
Time-tag controller logic
}
\label
{
fig:timetag-core
}
\end{figure}
A free-running counter inside the block counts the ticks of the
\textit
{
clk
\_
i
}
signal
to count the seconds. When it reaches the value
\textit
{
g
\_
clk
\_
rate-1
}
(125~mega in
the figure), it resets and sends a "tick" to the TAI seconds counter, which then increments.
As seen in Figure~
\ref
{
fig:hdl-bd
}
, the pulse inputs are derived from the OR gate which
ORs together the TTL and blocking inputs. Since these pulses can be asynchronous, they
are synchronized in the 125~MHz domain and passed through rising edge detectors. A rising
edge on any channel then triggers the
\textit
{
fifo
\_
wr
\_
req
\_
p
\_
o
}
output. As the port's
name suggests, this signal is a one-cycle pulse that triggers a write to the FIFO. Note
that the
\textit
{
fifo
\_
full
\_
i
}
signal is also checked prior to triggering a write to the
FIFO. This is not shown in Figure~
\ref
{
fig:timetag-core
}
in order to simplify it.
are synchronized in the 125~MHz domain and passed through rising edge detectors. If the
FIFO is not full, a rising edge on any channel then triggers the
\textit
{
fifo
\_
wr
\_
req
\_
p
\_
o
}
output. As the port's name suggests, this signal is a one-cycle
pulse that triggers a write to the FIFO.
Note that due to the synchronization logic, rising edge detector and the latching of the
ORed pulse rising edge detection signal, the
\textit
{
fifo
\_
wr
\_
req
\_
p
\_
o
}
signal is
set between three and four cycles after the pulse signal actually arrives on the input.
All the output ports are connected externally directly to the FIFO, therefore when the
\textit
{
fifo
\_
wr
\_
req
\_
p
\_
o
}
output pulses, they are written to the FIFO. As shown in
...
...
@@ -795,6 +809,15 @@ board status register (SR -- see Appendix~\ref{app:conv-regs-sr}).
The FIFO itself is generated using
\textit
{
wbgen2
}
~
\cite
{
wbgen2
}
and connected
on the top-level to the
\textit
{
pulse
\_
timetag
}
component.
Due to the two clock domains in the design, some synchronization logic is needed. This is
achieved via
\textit
{
gc
\_
sync
\_
ffs
}
components from the
\textit
{
general-cores
}
library~
\cite
{
gencores-ohwr
}
in the case of the WR time valid signals storage to the SR
and in the case of the TAI time value load pulses from the
\textit
{
conv
\_
regs
}
to the
\textit
{
pulse
\_
timetag
}
components.
The TAI time signal is not synchronized before being connected to the
\textit
{
conv
\_
regs
}
component, since its rate of change of once per second is considered too slow to present
any problem of synchronization when read by the user.
%======================================================================================
% SEC: Folder structure
...
...
modules/Release/conv_pulse_gen.vhd
View file @
b7a79518
...
...
@@ -47,6 +47,8 @@
-- 02-08-2013 Theodor Stana Implemented rejection phase.
-- 17-02-2014 Theodor Stana Moved the glitch filter to outside the
-- module.
-- 04-03-2014 Theodor Stana Added first pulse inhibit on glitch-filtered
-- side.
--==============================================================================
-- TODO: -
--==============================================================================
...
...
@@ -157,6 +159,9 @@ architecture behav of conv_pulse_gen is
signal
pulse_gf_off
:
std_logic
;
signal
pulse_gf_off_rst
:
std_logic
;
-- Inhibit first pulse
signal
inh_fp_gf_on
:
std_logic
;
-- Pulse length counter
signal
pulse_cnt
:
unsigned
(
f_log2_size
(
6
*
g_pwidth
)
-1
downto
0
);
...
...
@@ -221,11 +226,22 @@ begin
pulse_gf_on
<=
'0'
;
pulse_cnt
<=
(
others
=>
'0'
);
trig_gf_on_d0
<=
'0'
;
inh_fp_gf_on
<=
'1'
;
elsif
(
en_i
=
'1'
)
then
-- Deglitched trigger delay
-- Deglitched trigger delay
.
trig_gf_on_d0
<=
trig_gf_on
;
-- State machine
-- On the first cycle after the reset, the pulse channel needs to be
-- inhibited when the converter board is in TTL-BAR repetition mode,
-- since in this mode, an unconnected channel is HIGH for the first
-- 100us until the "no signal detect" block triggers, and the HIGH level
-- on the line will get interpreted by the trigger delay (due to its reset
-- state) as a rising edge on the line, thus triggering a pulse.
if
inh_fp_gf_on
=
'1'
then
inh_fp_gf_on
<=
'0'
;
end
if
;
-- State machine logic
case
state
is
---------------------------------------------------------------------
-- IDLE
...
...
@@ -241,7 +257,8 @@ begin
state
<=
GEN_GF_OFF
;
end
if
;
else
if
(
trig_gf_on
=
'1'
)
and
(
trig_gf_on_d0
=
'0'
)
then
if
(
trig_gf_on
=
'1'
)
and
(
trig_gf_on_d0
=
'0'
)
and
(
inh_fp_gf_on
=
'0'
)
then
state
<=
GEN_GF_ON
;
end
if
;
end
if
;
...
...
syn/Release/Makefile
View file @
b7a79518
...
...
@@ -22,164 +22,3 @@ clean:
mrproper
:
rm
-f
*
.bit
*
.bin
*
.mcs
USER
:=
$(HDLMAKE_USER)
#take the value from the environment
SERVER
:=
$(HDLMAKE_SERVER)
#take the value from the environment
R_NAME
:=
conv_ttl_blo
__test_for_remote_synthesis_variables
:
ifeq
(x$(USER),x)
@echo
"Remote synthesis user is not set. You can set it by editing variable USER in the makefile."
&&
false
endif
ifeq
(x$(SERVER),x)
@echo
"Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile."
&&
false
endif
CWD
:=
$(
shell
pwd
)
FILES
:=
../../top/Release/conv_ttl_blo.ucf
\
../../top/Release/conv_ttl_blo.vhd
\
../../modules/Release/conv_regs.vhd
\
../../modules/Release/conv_pulse_gen.vhd
\
../../modules/Release/conv_man_trig.vhd
\
../../modules/Release/pulse_timetag.vhd
\
../../modules/reset_gen.vhd
\
../../modules/rtm_detector.vhd
\
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
\
../../ip_cores/general-cores/modules/common/gc_reset.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
\
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
\
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
\
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
\
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
\
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd
\
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd
\
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
\
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd
\
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd
\
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd
\
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
\
run.tcl
\
conv_ttl_blo.xise
#target for running simulation in the remote location
remote
:
__test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back
:
__do_synthesis
__do_synthesis
:
__send
__send
:
__test_for_remote_synthesis_variables
__send
:
ssh
$(USER)
@
$(SERVER)
'mkdir -p
$(R_NAME)
'
rsync
-Rav
$
(
foreach file,
$(FILES)
,
$(
shell
readlink
-f
$(file))
)
$(USER)
@
$(SERVER)
:
$(R_NAME)
__do_synthesis
:
ssh
$(USER)
@
$(SERVER)
'cd
$(R_NAME)$(CWD)
&& xtclsh run.tcl'
__send_back
:
cd
..
&&
rsync
-av
$(USER)
@
$(SERVER)
:
$(R_NAME)$(CWD)
.
&&
cd
$(CWD)
#target for removing stuff from the remote location
cleanremote
:
ssh
$(USER)
@
$(SERVER)
'rm -rf
$(R_NAME)
'
syn/Release/conv_ttl_blo.xise
View file @
b7a79518
...
...
@@ -341,16 +341,16 @@
<file
xil_pn:name=
"../../top/Release/conv_ttl_blo.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
</file>
<file
xil_pn:name=
"../../
top/Release/conv_ttl_blo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/genrams/genram_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
</file>
<file
xil_pn:name=
"../../
modules/Release/conv_regs
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3"
/>
</file>
<file
xil_pn:name=
"../../modules/Release/conv_pulse_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4"
/>
</file>
<file
xil_pn:name=
"../../
modules/Release/conv_man_tri
g.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/common/gencores_pk
g.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5"
/>
</file>
<file
xil_pn:name=
"../../modules/Release/pulse_timetag.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -362,7 +362,7 @@
<file
xil_pn:name=
"../../modules/rtm_detector.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
common/gencores
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/
wishbone/wishbone
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -422,7 +422,7 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"28"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/genrams/genram_pk
g.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/Release/conv_man_tri
g.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"29"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -437,7 +437,7 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"33"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wishbone
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/bicolor_led_ctrl/bicolor_led_ctrl
_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"34"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -521,10 +521,10 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"61"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_
wb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_
pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"62"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_
pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_
wb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"63"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -569,7 +569,7 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"77"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_
timer
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_
pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"78"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -584,7 +584,7 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"82"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_
pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_
timer
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"83"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -668,16 +668,16 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"110"
/>
</file>
<file
xil_pn:name=
"../../
ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
modules/Release/conv_regs
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"111"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/
wb_xilinx_fpga_loader
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/
xloader_registers_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"112"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"113"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/
xloader_registers_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/
wb_xilinx_fpga_loader
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"114"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
@@ -695,7 +695,7 @@
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"119"
/>
</file>
<file
xil_pn:name=
"../../
modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../
top/Release/conv_ttl_blo
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"120"
/>
</file>
<file
xil_pn:name=
"../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
...
...
top/Release/conv_ttl_blo.vhd
View file @
b7a79518
...
...
@@ -59,7 +59,8 @@ entity conv_ttl_blo is
generic
(
g_nr_ttl_chan
:
natural
:
=
6
;
g_nr_inv_chan
:
natural
:
=
4
g_nr_inv_chan
:
natural
:
=
4
;
g_sim
:
boolean
:
=
false
);
port
(
...
...
@@ -161,6 +162,21 @@ architecture behav of conv_ttl_blo is
type
t_pulse_cnt
is
array
(
1
to
g_nr_ttl_chan
)
of
unsigned
(
31
downto
0
);
type
t_ch_pcr
is
array
(
1
to
g_nr_ttl_chan
)
of
std_logic_vector
(
31
downto
0
);
--============================================================================
-- Function and procedure declarations
--============================================================================
function
f_reset_width
return
positive
is
variable
retval
:
positive
;
begin
retval
:
=
2
*
(
10
**
6
);
if
g_sim
then
retval
:
=
20
;
end
if
;
assert
false
report
"Reset width: "
&
integer
'image
(
retval
)
&
"*50ns"
severity
Note
;
return
retval
;
end
function
f_reset_width
;
--============================================================================
-- Constant declarations
--============================================================================
...
...
@@ -529,12 +545,12 @@ architecture behav of conv_ttl_blo is
signal
trig_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_ttl_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_blo_a
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_degl
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced_r_edge_p
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_synced
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig
_degl
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_chan
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
trig_man
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pgen_trig
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
signal
pcnt_trig_p
:
std_logic_vector
(
g_nr_ttl_chan
downto
1
);
-- TTL-BAR lack of signal counter
signal
ttlbar_nosig_cnt
:
t_ttlbar_nosig_cnt
;
...
...
@@ -615,7 +631,7 @@ begin
generic
map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time
=>
2
*
(
10
**
6
)
g_reset_time
=>
f_reset_width
)
port
map
(
...
...
@@ -909,35 +925,7 @@ begin
-- TTL and blocking pulse generation logic
--============================================================================
------------------------------------------------------------------------------
-- TTL and blocking inputs, input GF and input channel MUX based on GF switch
------------------------------------------------------------------------------
trig_ttl_a
<=
not
fpga_input_ttl_n_i
when
(
ttl_switch_n_i
=
'0'
)
else
fpga_input_ttl_n_i
and
ttlbar_nosig_n
;
trig_blo_a
<=
fpga_blo_in_i
;
trig_a
<=
trig_ttl_a
or
trig_blo_a
;
-- Input channel glitch filter
gen_glitch_filt
:
for
i
in
1
to
g_nr_ttl_chan
generate
cmp_inp_glitch_filt
:
gc_glitch_filt
generic
map
(
g_len
=>
c_pulse_gen_gf_len
)
port
map
(
clk_i
=>
clk_20_vcxo_i
,
rst_n_i
=>
rst_20_n
,
dat_i
=>
trig_a
(
i
),
dat_o
=>
trig_degl
(
i
)
);
end
generate
gen_glitch_filt
;
-- Channel trigger MUX
trig_chan
<=
trig_a
when
extra_switch_n_i
(
1
)
=
'1'
else
trig_degl
;
------------------------------------------------------------------------------
-- Pulse time-tagging logic after input channale MUX
-- Pulse time-tagging logic after input channel MUX
------------------------------------------------------------------------------
cmp_pulse_timetag
:
pulse_timetag
generic
map
...
...
@@ -1001,29 +989,96 @@ begin
trig_o
=>
trig_man
);
------------------------------------------------------------------------------
-- FINALLY, the trigger input to the pulse generator block
------------------------------------------------------------------------------
trig
<=
trig_chan
or
trig_man
;
------------------------------------------------------------------------------
-- Generate pulse repetition logic
------------------------------------------------------------------------------
gen_pulse_logic
:
for
i
in
1
to
g_nr_ttl_chan
generate
-- First, resync the trigger signal into clk_20_vcxo_i domain
-- First, the "no signal detect" blocks
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
p_ttlbar_nosig
:
process
(
clk_20_vcxo_i
)
begin
if
rising_edge
(
clk_20_vcxo_i
)
then
if
(
rst_20_n
=
'0'
)
or
(
fpga_input_ttl_n_i
(
i
)
=
'0'
)
then
ttlbar_nosig_n
(
i
)
<=
'1'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
elsif
(
ttl_switch_n_i
=
'1'
)
then
ttlbar_nosig_cnt
(
i
)
<=
ttlbar_nosig_cnt
(
i
)
+
1
;
if
(
ttlbar_nosig_cnt
(
i
)
=
1999
)
then
ttlbar_nosig_n
(
i
)
<=
'0'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
process
p_ttlbar_nosig
;
-- The first OR gate at the channel inputs
trig_ttl_a
(
i
)
<=
not
fpga_input_ttl_n_i
(
i
)
when
(
ttl_switch_n_i
=
'0'
)
else
fpga_input_ttl_n_i
(
i
)
and
ttlbar_nosig_n
(
i
);
trig_blo_a
(
i
)
<=
fpga_blo_in_i
(
i
);
trig_a
(
i
)
<=
trig_ttl_a
(
i
)
or
trig_blo_a
(
i
);
-- Then, synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_trig_sync
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
(
clk_i
=>
clk_20_vcxo_i
,
rst_n_i
=>
'1'
,
data_i
=>
trig_a
(
i
),
synced_o
=>
trig_synced
(
i
)
);
-- Deglitch synchronized trigger signal
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_inp_glitch_filt
:
gc_glitch_filt
generic
map
(
g_len
=>
c_pulse_gen_gf_len
)
port
map
(
clk_i
=>
clk_20_vcxo_i
,
rst_n_i
=>
'1'
,
dat_i
=>
trig_synced
(
i
),
dat_o
=>
trig_degl
(
i
)
);
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan
(
i
)
<=
trig_a
(
i
)
when
extra_switch_n_i
(
1
)
=
'1'
else
trig_degl
(
i
);
-- Now, sync this channel trigger signal before passing it to the counters
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
--
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and has no
-- influence on the correctness of the pulse counter value considering the
-- max expected pulse frequency
cmp_sync_ffs
:
gc_sync_ffs
cmp_sync_ffs
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_20_vcxo_i
,
rst_n_i
=>
'1'
,
data_i
=>
trig_chan
(
i
),
synced_o
=>
trig_synced
(
i
),
ppulse_o
=>
trig_synced_r_edge_p
(
i
)
ppulse_o
=>
pcnt_trig_p
(
i
)
);
-- Then, generate the input pulse counters
...
...
@@ -1034,34 +1089,14 @@ begin
pulse_cnt
(
i
)
<=
(
others
=>
'0'
);
elsif
(
ch_pcr_ld
(
i
)
=
'1'
)
then
pulse_cnt
(
i
)
<=
unsigned
(
ch_pcr
(
i
));
elsif
(
trig_synced_r_edge
_p
(
i
)
=
'1'
)
then
elsif
(
pcnt_trig
_p
(
i
)
=
'1'
)
then
pulse_cnt
(
i
)
<=
pulse_cnt
(
i
)
+
1
;
end
if
;
end
if
;
end
process
p_pulse_cnt
;
-- Process to detect lack of signal on TTL line
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
-- the mux input.
--
-- Counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption from the counter.
p_ttlbar_nosig
:
process
(
clk_20_vcxo_i
)
begin
if
rising_edge
(
clk_20_vcxo_i
)
then
if
(
rst_20_n
=
'0'
)
or
(
fpga_input_ttl_n_i
(
i
)
=
'0'
)
then
ttlbar_nosig_n
(
i
)
<=
'1'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
elsif
(
ttl_switch_n_i
=
'1'
)
then
ttlbar_nosig_cnt
(
i
)
<=
ttlbar_nosig_cnt
(
i
)
+
1
;
if
(
ttlbar_nosig_cnt
(
i
)
=
1999
)
then
ttlbar_nosig_n
(
i
)
<=
'0'
;
ttlbar_nosig_cnt
(
i
)
<=
(
others
=>
'0'
);
end
if
;
end
if
;
end
if
;
end
process
p_ttlbar_nosig
;
-- FINALLY, the trigger input to the pulse generator block
pgen_trig
(
i
)
<=
trig_chan
(
i
)
or
trig_man
(
i
);
-- Output pulse generators
cmp_pulse_gen
:
conv_pulse_gen
...
...
@@ -1075,7 +1110,7 @@ begin
rst_n_i
=>
rst_20_n
,
en_i
=>
'1'
,
gf_en_n_i
=>
extra_switch_n_i
(
1
),
trig_a_i
=>
trig
(
i
),
trig_a_i
=>
pgen_
trig
(
i
),
pulse_o
=>
pulse_outp
(
i
)
);
...
...
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