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Conv TTL Blocking - Gateware
Commit b488cf13 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Added manual triggering to hdlguide 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent c74ddcd8
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doc/hdlguide/cern-title.tex
View file @ b488cf13
......@@ -9,9 +9,9 @@
\noindent \rule{\textwidth}{.1cm}
\hfill Gateware v1.1
\hfill Gateware v1.2
\hfill January 28, 2014
\hfill January 30, 2014
\vspace*{3cm}
......
doc/hdlguide/fig/hdl-bd.svg
View file @ b488cf13
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
View file @ b488cf13
......@@ -61,6 +61,7 @@
20-11-2013 & 1.04 & Changed system clock to 20~MHz \\
05-01-2014 & 1.05 & Updated folder structure and renamed \textit{vbcp\_wb} to \textit{i2c\_bridge} \\
28-01-2014 & 1.06 & Added pulse counters in HDL \\
30-01-2014 & 1.07 & Added manual pulse triggering in HDL \\
\hline
\end{tabular}
}
......@@ -106,18 +107,20 @@ the CONV-TTL-BLO capabilities:
\begin{itemize}
\item pulse detection (on pulse rising edge)
\item fixed-width pulse generation with pulse rejection
\item status retrieval (diagnostics) via I$^2$C
\item diagnostics via I$^2$C
\begin{itemize}
\item gateware version
\item switches and RTM detection lines
\item pulse counters
\item remote reset
\item manual pulse triggering
\end{itemize}
\item remote reprogramming via I$^2$C
\end{itemize}
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL gateware. Each of the
blocks in the figure is presented in following sections.
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL gateware. The
blocks in this figure implemented as part of the CONV-TTL-BLO gateware are presented
in the sections that follow.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/hdl-bd}}
......@@ -138,7 +141,7 @@ blocks in the figure is presented in following sections.
%==============================================================================
% SEC: Clocks
%==============================================================================
\section{FPGA Clocks}
\section{FPGA clocks}
\label{sec:clocks}
There are two clock signals input to the FPGA (Figure~\ref{fig:clocks}).
......@@ -171,29 +174,88 @@ Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
}
\end{table}
%==============================================================================
% SEC: Mem-mapped periphs
%==============================================================================
\section{Memory-mapped peripherals}
\label{sec:periphs}
This section details the various peripherals mapped on the internal
Wishbone bus. Access to these peripherals is made through the two serial lines
on the VME P1 connector (SERCLK, SERDAT). A protocol based on I$^2$C is used to
access these peripherals. The protocol, as well as the bridge component
translating I$^2$C accesses into Wishbone accesses, are defined in the bridge
component's documentation.
The complete memory map of the gateware can be found in Appendix~\ref{app:memmap}.
%------------------------------------------------------------------------------
% SUBSEC: Bridge
%------------------------------------------------------------------------------
\subsection{I$^2$C to Wishbone bridge}
\label{sec:i2c-bridge}
The \textit{wb\_i2c\_bridge} module implements a bridge to translate I$^2$C accesses
on the VME P1 connector into Wishbone accesses on the FPGA. The module provides
one I$^2$C slave interface for connecting to an ELMA SysMon and one Wishbone
master interface.
Details about the module's implementation can be found in its documentation.
%------------------------------------------------------------------------------
% SUBSEC: conv_regs
%------------------------------------------------------------------------------
\subsection{Converter board registers}
\label{sec:periphs-conv-regs}
A set of registers are implemented as general-purpose registers for converter boards.
These are status and control registers implemented utilizing \textit{wbgen2}~\cite{wbgen2}.
Appendix~\ref{app:memmap-conv-regs} presents the converter board registers.
On the status registers side, there is one general status register (SR -- see
Appendix~\ref{app:memmap-sr}) that contains details about the gateware version,
the state of the on-board switches and RTM detection lines, as well as the state
of the communication watchdog timer. Then, there are six pulse counter registers
(CHxPCR -- see Appendix~\ref{app:memmap-chpcr}), one per each channel, which are updated
with the current values of the input pulse counters.
The logic also contains one control register (CR -- see Appendix~\ref{app:memmap-cr}),
which contains two bits for remotely resetting the FPGA logic.
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\subsection{MultiBoot control}
\label{sec:periphs-multiboot}
The MultiBoot module offers the remote reprogramming capabilities for the
CONV-TTL-BLO board. It offers a set of registers for controlling writing a bitstream
to the M25P32 flash chip and for issuing the remote reprogramming command.
For information on the module, refer to its documentation. The memory map of the
module is also present in this manual, for quick reference (see
Appendix~\ref{app:memmap-multiboot}).
%==============================================================================
% SEC: Reset gen
%==============================================================================
\section{Reset generator}
\label{sec:reset-gen}
%\begin{table}[h]
% \caption{Reset generator}
% \label{tbl:pulse-gen}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{reset\_gen} & \\
\textbf{Generics} & \textit{g\_reset\_time} & Reset time in \textit{clk\_i} cycles \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_i} & Active-high reset input \\
& \textit{rst\_n\_o} & Active-low reset output \\
\textbf{Usage} & Global reset generation & 100~$ms$ reset \\
\hline
\end{tabular}
}
%\end{table}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{reset\_gen} & \\
\textbf{Generics} & \textit{g\_reset\_time} & Reset time in \textit{clk\_i} cycles \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_i} & Active-high reset input \\
& \textit{rst\_n\_o} & Active-low reset output \\
\textbf{Usage} & Global reset generation & 100~$ms$ reset \\
\hline
\end{tabular}
}
\vspace*{11pt}
......@@ -227,23 +289,19 @@ By default, the reset time is set to 100~$ms$.
\section{RTM detection}
\label{sec:rtm-detect}
%\begin{table}[h]
% \caption{RTM detection block}
% \label{tbl:pulse-gen}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{rtm\_detector} & \\
\textbf{Ports} & \textit{rtmm\_i(2..0)} & RTM mainboard detection lines \\
& \textit{rtmp\_i(2..0)} & RTM piggyback detection lines \\
& \textit{rtmm\_ok\_o} & RTM mainboard present \\
& \textit{rtmp\_ok\_o} & RTM piggyback present \\
\textbf{Usage} & Light ERR status LED & \\
\hline
\end{tabular}
}
%\end{table}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{rtm\_detector} & \\
\textbf{Ports} & \textit{rtmm\_i(2..0)} & RTM mainboard detection lines \\
& \textit{rtmp\_i(2..0)} & RTM piggyback detection lines \\
& \textit{rtmm\_ok\_o} & RTM mainboard present \\
& \textit{rtmp\_ok\_o} & RTM piggyback present \\
\textbf{Usage} & Light ERR status LED & \\
\hline
\end{tabular}
}
\vspace*{11pt}
......@@ -269,30 +327,27 @@ can also be read via their respective fields in the converter board status regis
\section{Bicolor LED controller}
\label{sec:bicolor-led}
%\begin{table}[h]
% \caption{Bicolor LED controller block}
% \label{tbl:pulse-gen}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{bicolor\_led\_ctrl} & \\
\textbf{Generics} & \textit{g\_NB\_COLUMN} & Number of columns \\
& \textit{g\_NB\_LINE} & Number of lines \\
& \textit{g\_CLK\_FREQ} & Frequency (in Hz) of \textit{clk\_i} signal \\
& \textit{g\_REFRESH\_RATE} & LED refresh rate (in Hz)\\
\textbf{Ports} & \textit{rst\_n\_i} & Active-low reset input \\
& \textit{clk\_i} & Clock signal input \\
& \textit{led\_intensity\_i(6..0)} & 7-bit LED intensity vector \\
& \textit{led\_state\_i(..)} & LED state vector, two bits per LED \\
& \textit{column\_o(..)} & LED column vector, one bit per column \\
& \textit{line\_o(..)} & LED line vector, one bit per line \\
& \textit{line\_oen\_o(..)} & LED line enable vector, one bit per line\\
\textbf{Usage} & Light bicolor LEDS & \\
\hline
\end{tabular}
}
%\end{table}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{bicolor\_led\_ctrl} & \\
\textbf{Generics} & \textit{g\_NB\_COLUMN} & Number of columns \\
& \textit{g\_NB\_LINE} & Number of lines \\
& \textit{g\_CLK\_FREQ} & Frequency (in Hz) of \textit{clk\_i} signal \\
& \textit{g\_REFRESH\_RATE} & LED refresh rate (in Hz)\\
\textbf{Ports} & \textit{rst\_n\_i} & Active-low reset input \\
& \textit{clk\_i} & Clock signal input \\
& \textit{led\_intensity\_i(6..0)} & 7-bit LED intensity vector \\
& \textit{led\_state\_i(..)} & LED state vector, two bits per LED \\
& \textit{column\_o(..)} & LED column vector, one bit per column \\
& \textit{line\_o(..)} & LED line vector, one bit per line \\
& \textit{line\_oen\_o(..)} & LED line enable vector, one bit per line\\
\textbf{Usage} & Light bicolor LEDS & \\
\hline
\end{tabular}
}
\vspace*{11pt}
......@@ -389,27 +444,24 @@ selection signals to these multiplexers are set throughout the logic.
\section{Pulse generator}
\label{sec:pulse-gen}
%\begin{table}[h]
% \caption{Pulse generator blocks}
% \label{tbl:pulse-gen}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{conv\_pulse\_gen} & \\
\textbf{Generics} & \textit{g\_pwidth} & Width of the output pulse in \textit{clk\_i} cycles \\
& \textit{g\_gf\_len} & Length of glitch filter in \textit{clk\_i} cycles \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\
& \textit{gf\_en\_n\_i} & Active-low glitch filter enable \\
& \textit{trig\_i} & Pulse trigger \\
& \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~$\mu$s pulses with min. period of 6~$\mu$s\\
\hline
\end{tabular}
}
%\end{table}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{conv\_pulse\_gen} & \\
\textbf{Generics} & \textit{g\_pwidth} & Width of the output pulse in \textit{clk\_i} cycles \\
& \textit{g\_gf\_len} & Length of glitch filter in \textit{clk\_i} cycles \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\
& \textit{gf\_en\_n\_i} & Active-low glitch filter enable \\
& \textit{trig\_i} & Pulse trigger \\
& \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~$\mu$s pulses with min. period of 6~$\mu$s \\
& & and one-cycle wide glitch filter \\
\hline
\end{tabular}
}
\vspace*{11pt}
......@@ -486,10 +538,9 @@ in the code. These constants assure the pulse at the output is kept high for a n
Figure~\ref{fig:pulse-brd} shows the pulse replication mechanism on the
CONV-TTL-BLO. Here, the \textit{PG} block is the \textit{conv\_pulse\_gen} block
with the necessary settings. Since the \textit{conv\_pulse\_gen} block expects
a rising edge at its \textit{trig\_i} input in order to generate a pulse at
the output, logic external to the block caters for the different types of signals
that arrive on CONV-TTL-BLO inputs.
with the necessary settings. This block can either be triggered via a pulse arriving
on the TTL or blocking channel, or by a manual trigger pulse arriving from the
\textit{conv\_man\_trig} component (see Section~\ref{sec:man-trig}).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-rep}}
......@@ -497,11 +548,16 @@ that arrive on CONV-TTL-BLO inputs.
\label{fig:pulse-brd}
\end{figure}
\pagebreak
Since the \textit{conv\_pulse\_gen} block expects a rising edge at its \textit{trig\_i}
input in order to generate a pulse at the output, logic external to the block
caters for the different types of signals that arrive on CONV-TTL-BLO inputs.
Most of this external logic is on the TTL pulse side, where both TTL and TTL-BAR
pulses may arrive. As described in Section 4.3 of \cite{ctb-ug}, if a wire is not plugged in
when TTL-BAR pulses are input, a continuous logic high level on the line would inhibit
pulses arriving on the blocking side from triggering a pulse generation. This is why
the \textit{no signal detect} block has been implemented.
pulses may arrive. As described in Section 4.3 of the CONV-TTL-BLO User Guide\cite{ctb-ug},
if a wire is not plugged in when TTL-BAR pulses are input, a continuous logic high level
on the line would inhibit pulses arriving on the blocking side from triggering a pulse
generation. This is why the \textit{no signal detect} block has been implemented.
The block's implementation is shown in Figure~\ref{fig:no-sig-detect}. It is implemented as
a counter which keeps the \textit{en\_o} signal high as long as it does not reach its maximum value.
......@@ -546,72 +602,84 @@ the value received via I$^2$C.
\end{figure}
%==============================================================================
% SEC: Mem-mapped periphs
% SEC: Manual trigger
%==============================================================================
\section{Memory-mapped peripherals}
\label{sec:periphs}
This section details the various peripherals mapped on the internal
Wishbone bus. Access to these peripherals is made through the two serial lines
on the VME P1 connector (SERCLK, SERDAT). A protocol based on I$^2$C is used to
access these peripherals. The protocol, as well as the bridge component
translating I$^2$C accesses into Wishbone accesses, are defined in the bridge
component's documentation.
The complete memory map of the gateware can be found in Appendix~{app:memmap}.
%------------------------------------------------------------------------------
% SUBSEC: Statregs
%------------------------------------------------------------------------------
\subsection{I$^2$C to Wishbone bridge}
\label{sec:i2c-bridge}
The \textit{i2c\_bridge} module implements a bridge to translate I$^2$C accesses
on the VME P1 connector into Wishbone accesses on the FPGA. The module provides
one I$^2$C slave interface for connecting to an ELMA SysMon and one Wishbone
master interface.
Details about the module's implementation can be found in its documentation.
%------------------------------------------------------------------------------
% SUBSEC: CSR
%------------------------------------------------------------------------------
\subsection{Converter board registers}
\label{sec:periphs-conv-regs}
A set of registers are implemented as general-purpose registers for converter boards.
These are status and control registers implemented utilizing \textit{wbgen2}~\cite{wbgen2}.
Appendix~\ref{app:memmap-conv-regs} presents the converter board registers.
\section{Manual pulse trigger}
\label{sec:man-trig}
On the status registers side, there is one general status register (SR -- see
Appendix~\ref{app:memmap-sr}) that contains details about the gateware version,
the state of the on-board switches and RTM detection lines, as well as the state
of the communication watchdog timer. Then, there are six pulse counter registers
(CHxPCR -- see Appendix~\ref{app:memmap-chpcr}), one per each channel, which are updated
with the current values of the input pulse counters.
The logic also contains one control register (CR -- see Appendix~\ref{app:memmap-cr}),
which contains two bits for remotely resetting the FPGA logic.
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{conv\_man\_trig} & \\
\textbf{Generics} & \textit{g\_nr\_chan} & Pulse repeater number of channels \\
& \textit{g\_gf\_len} & Pulse generator glitch filter length \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{reg\_ld\_i} & MPT in the CR written \\
& \textit{reg\_i} & Value of MPT field in the CR \\
& \textit{trig\_o} & Trigger output \\
\textbf{Usage} & Trigger pulse generator & Two clock-cycle pulse output \\
\hline
\end{tabular}
}
\vspace*{11pt}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\subsection{MultiBoot control}
\label{sec:periphs-multiboot}
The manual pulse triggering mechanism is achieved via the \textit{conv\_man\_trig}
module. This module generates a pulse that is input to the \textit{conv\_pulse\_gen}
module and that triggers a 1.2~$\mu$s pulse on the TTL and blocking outputs.
Since manual pulse generation is a delicate feature which is only used when a debug
pulse is generated on a channel, a "password" is needed in order to manually trigger
a pulse. This "password" is obtained from the MPT field in the control register
(CR -- see Appendix~\ref{app:memmap-cr}), where a magic sequence of
numbers should be written. Once this magic sequence has been input, the next write to
the register should be the channel number. If a valid channel number is written,
a pulse is generated on this channel.
The \textit{conv\_man\_trig} takes the value of the MPT field in the control register
as an input and via the state-machine shown in Figure~\ref{fig:man-trig-fsm}, it checks
that the values written to the MPT field correspond to the magic sequence (Table~\ref{tbl:man-trig-magic}).
The FSM advances on writes to the MPT field of the CR. Once the magic sequence has been received,
the next write to the MPT field sets the \textit{trig\_o} output, which is input to the \textit{trig\_i}
input of \textit{conv\_pulse\_gen} (see Section~\ref{sec:pulse-gen}) after it is ORed together with the
TTL and blocking inputs as shown in Figure~\ref{fig:pulse-brd}. Should an invalid channel number be
input, no error is reported and no pulse is generated.
\begin{figure}
\centerline{\includegraphics[width=.47\textwidth]{fig/man-trig-fsm}}
\caption{FSM of the \textit{conv\_man\_trig} component}
\label{fig:man-trig-fsm}
\end{figure}
The MultiBoot module offers the remote reprogramming capabilities for the
CONV-TTL-BLO board. It offers a set of registers for controlling writing a bitstream
to the M25P32 flash chip and for issuing the remote reprogramming command.
\begin{table}[h]
\caption{Magic sequence to initiate manual pulse triggering}
\label{tbl:man-trig-magic}
\centerline
{
\begin{tabular}{c c c c}
\hline
\textbf{Byte 0} & \textbf{Byte 1} & \textbf{Byte 2} & \textbf{Byte 3} \\
\hline
0xde & 0xad & 0xbe & 0xef \\
\hline
\end{tabular}
}
\end{table}
For information on the module, refer to its documentation. The memory map of the
module is also present in this manual, for quick reference (see
Appendix~\ref{app:memmap-multiboot}).
To generate a long enough pulse to be detected by the \textit{conv\_pulse\_gen} component
when its glitch filter is enabled, the \textit{conv\_man\_trig} should have knowledge
of the length of the pulse generator's glitch filter, which can be supplied via the
\textit{g\_gf\_len} generic. With the value of this generic, the \textit{conv\_man\_trig}
component extends the \textit{trig\_o} pulse to the necessary number of cycles for the
\textit{conv\_pulse\_gen} to detect a pulse. This extension is done in the \textit{GEN}
state (Figure~\ref{fig:man-trig-fsm}).
%======================================================================================
% SEC: Folder structure
%======================================================================================
\section{Folder Structure}
\section{Folder structure}
\label{sec:fold-struct}
Gateware files are organized on a per type-of-project basis. There are two different types of
......@@ -665,6 +733,8 @@ The folder structure for the project is presented below.
\begin{itemize}
\item Release/
\begin{itemize}
\item conv\_man\_trig.vhd
\item conv\_pulse\_gen.vhd
\item conv\_regs.vhd
\item conv\_regs.wb
\end{itemize}
......@@ -692,15 +762,15 @@ The folder structure for the project is presented below.
\item conv\_ttl\_blo.vhd
\end{itemize}
\item pulsetest/
% \begin{itemize}
% \item pulsetest.ucf
% \item pulsetest.vhd
% \end{itemize}
\begin{itemize}
\item pulsetest.ucf
\item pulsetest.vhd
\end{itemize}
\item regtest/
% \begin{itemize}
% \item pulsetest.ucf
% \item pulsetest.vhd
% \end{itemize}
\begin{itemize}
\item regtest.ucf
\item regtest.vhd
\end{itemize}
\end{itemize}
\end{itemize}
\end{itemize}
......@@ -747,7 +817,7 @@ the design and as such can be composed of folders named after the component to b
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\section{Getting Around the Code}
\section{Getting around the code}
\label{sec:get-around}
Ports and signals usually follow the coding guideline at~\cite{coding-guidelines}. Most of the
......@@ -952,7 +1022,8 @@ $reg. index = \frac{addr}{4} + 1$
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
0 & RST\_UNLOCK & R/W & 0 & Reset bit unlock \\
1 & RST & R/W & 0 & Reset bit \\
31..2 & \textit{Reserved} & -- & X & \\
9..2 & MPT & W/O & 0 & Manual Pulse Trigger control \\
31..10 & \textit{Reserved} & -- & X & \\
\end{tabular}
\noindent
......@@ -970,6 +1041,13 @@ $reg. index = \frac{addr}{4} + 1$
previous cycle. A write to this bit while RST\_UNLOCK = '0' has no effect. \newline
Writing this bit to 1 with RST\_UNLOCK = '1' will issue a system reset and
the communication to the board will be lost for approx. 100~ms \\
MPT & Control bits for manual pulse trigger sequence \newline
To trigger a pulse, write this sequence to the field: \newline
\textbf{0xde} -- Passbyte 1 \newline
\textbf{0xad} -- Passbyte 2 \newline
\textbf{0xbe} -- Passbyte 3 \newline
\textbf{0xef} -- Passbyte 4 \newline
Channel number in range 1..6 \\
\textit{Reserved} & Write as '0'; read undefined \\
\end{tabular}
}
......
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