Skip to content

C
Conv TTL Blocking - Gateware
Commit ad800f0c authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
Browse files
Options

Clean up of ./syn folder

parent b4f182b5
Hide whitespace changes
Inline Side-by-side
Showing with 0 additions and 8871869 deletions
syn/Release/.cxl.mti_se.version deleted 100644 → 0
View file @ b4f182b5
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
syn/Release/Makefile deleted 100644 → 0
View file @ b4f182b5
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo.xise
ISE_CRAP := *.b conv_ttl_blo_summary.html *.tcl conv_ttl_blo.bld conv_ttl_blo.cmd_log *.drc conv_ttl_blo.lso *.ncd conv_ttl_blo.ngc conv_ttl_blo.ngd conv_ttl_blo.ngr conv_ttl_blo.pad conv_ttl_blo.par conv_ttl_blo.pcf conv_ttl_blo.prj conv_ttl_blo.ptwx conv_ttl_blo.stx conv_ttl_blo.syr conv_ttl_blo.twr conv_ttl_blo.twx conv_ttl_blo.gise conv_ttl_blo.unroutes conv_ttl_blo.ut conv_ttl_blo.xpi conv_ttl_blo.xst conv_ttl_blo_bitgen.xwbt conv_ttl_blo_envsettings.html conv_ttl_blo_guide.ncd conv_ttl_blo_map.map conv_ttl_blo_map.mrp conv_ttl_blo_map.ncd conv_ttl_blo_map.ngm conv_ttl_blo_map.xrpt conv_ttl_blo_ngdbuild.xrpt conv_ttl_blo_pad.csv conv_ttl_blo_pad.txt conv_ttl_blo_par.xrpt conv_ttl_blo_summary.xml conv_ttl_blo_usage.xml conv_ttl_blo_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
syn/Release/Manifest.py deleted 100644 → 0
View file @ b4f182b5
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../../top/Release"
]
}
syn/Release/__Previews/conv_ttl_blo.tclPreview deleted 100644 → 0
View file @ b4f182b5
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/Release/_xmsgs/pn_parser (2).xmsgs deleted 100644 → 0
View file @ b4f182b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
</messages>
syn/Release/compxlib.cfg deleted 100644 → 0
View file @ b4f182b5
#*****************************************************************
# C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe configuration file - compxlib.cfg
# Tue Sep 06 17:17:54 2016
#
# Important :-
# All options/variables must start from first column
#
#*****************************************************************
#
RELEASE_VERSION:14.7
#
RELEASE_BUILD:P.20131013
#
# set current simulator name
SIMULATOR_NAME:mti_se
#
# set current language name
LANGUAGE_NAME:all
#
# set compilation execution mode
EXECUTE:on
#
# print compilation command template in log file
LOG_CMD_TEMPLATE:off
#
# Hierarchical Output Directories
HIER_OUT_DIR:off
#
# print Pre-Compiled library info
PRECOMPILED_INFO:on
#
# create backup copy of setup files
BACKUP_SETUP_FILES:on
#
# use enhanced compilation techniques for faster library compilation
# (applicable to selected libraries only)
FAST_COMPILE:on
#
# save compilation results to log file with the name specified with -log option
ADD_COMPILATION_RESULTS_TO_LOG:on
#
# abort compilation process if errors are detected in the library
ABORT_ON_ERROR:off
#
# compile library in the directory specified by the environment variable if the
# -dir option is not specified
OUTPUT_DIR_ENV:
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim SE
SET:mti_se:MODELSIM=modelsim.ini
#
# ModelSim SE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_se:vhdl:u:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:s:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:c:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:r:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:i:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim SE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_se:verilog:u:-source -novopt
OPTION:mti_se:verilog:s:-source -novopt
OPTION:mti_se:verilog:n:-source -novopt
OPTION:mti_se:verilog:c:-source -novopt
OPTION:mti_se:verilog:r:-source -novopt
OPTION:mti_se:verilog:i:-source -novopt
OPTION:mti_se:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim PE
SET:mti_pe:MODELSIM=modelsim.ini
#
# ModelSim PE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_pe:vhdl:u:-source -93 -explicit
OPTION:mti_pe:vhdl:s:-source -93 -explicit
OPTION:mti_pe:vhdl:c:-source -93 -explicit
OPTION:mti_pe:vhdl:r:-source -93 -explicit
OPTION:mti_pe:vhdl:i:-source -93 -explicit
OPTION:mti_pe:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim PE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_pe:verilog:u:-source
OPTION:mti_pe:verilog:s:-source
OPTION:mti_pe:verilog:n:-source
OPTION:mti_pe:verilog:c:-source
OPTION:mti_pe:verilog:r:-source
OPTION:mti_pe:verilog:i:-source
OPTION:mti_pe:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim DE
SET:mti_de:MODELSIM=modelsim.ini
#
# ModelSim DE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_de:vhdl:u:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:s:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:c:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:r:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:i:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim DE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_de:verilog:u:-source -novopt
OPTION:mti_de:verilog:s:-source -novopt
OPTION:mti_de:verilog:n:-source -novopt
OPTION:mti_de:verilog:c:-source -novopt
OPTION:mti_de:verilog:r:-source -novopt
OPTION:mti_de:verilog:i:-source -novopt
OPTION:mti_de:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: QuestaSim
SET:questasim:MODELSIM=modelsim.ini
#
# QuestaSim options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:questasim:vhdl:u:-source -93 -novopt -explicit
OPTION:questasim:vhdl:s:-source -93 -novopt -explicit
OPTION:questasim:vhdl:c:-source -93 -novopt -explicit
OPTION:questasim:vhdl:r:-source -93 -novopt -explicit
OPTION:questasim:vhdl:i:-source -93 -novopt -explicit
OPTION:questasim:vhdl:e:-93 -novopt -quiet -explicit
#
# QuestaSim options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:questasim:verilog:u:-source -novopt
OPTION:questasim:verilog:s:-source -novopt
OPTION:questasim:verilog:n:-source -novopt
OPTION:questasim:verilog:c:-source -novopt
OPTION:questasim:verilog:r:-source -novopt
OPTION:questasim:verilog:i:-source -novopt
OPTION:questasim:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: Aldec
SET:riviera:LIBRARY=library.cfg
#
# Aldec options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:riviera:vhdl:u:-93
OPTION:riviera:vhdl:s:-93
OPTION:riviera:vhdl:c:-93
OPTION:riviera:vhdl:r:-93
OPTION:riviera:vhdl:i:-93
OPTION:riviera:vhdl:e:-93
#
# Aldec options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:riviera:verilog:u:-v2k5
OPTION:riviera:verilog:s:-v2k5
OPTION:riviera:verilog:n:-v2k5
OPTION:riviera:verilog:c:-v2k5
OPTION:riviera:verilog:r:-v2k5
OPTION:riviera:verilog:i:-v2k5
OPTION:riviera:verilog:e:-v2k5
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: Aldec
SET:active_hdl:LIBRARY=library.cfg
#
# Aldec options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:active_hdl:vhdl:u:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:s:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:c:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:r:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:i:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:e:-93 -quiet -nowarn ELAB1_0026
#
# Aldec options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:active_hdl:verilog:u:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:s:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:n:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:c:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:r:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:i:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:e:-v2k5 -quiet -msg 0
#///////////////////////////////////////////////////////////////////////
# End
syn/Release/conv_burst_ctrl_vhdl.prj deleted 100644 → 0
View file @ b4f182b5
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\genrams\genram_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\wishbone\wishbone_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\top\conv_common_gw_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\common\gencores_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\common\gc_sync_ffs.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_burst_ctrl.vhd"
syn/Release/conv_common_gw_beh.prj deleted 100644 → 0
View file @ b4f182b5
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
verilog work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
syn/Release/conv_dyn_burst_ctrl.udo deleted 100644 → 0
View file @ b4f182b5
######################################################################
##
## Filename: conv_dyn_burst_ctrl.udo
## Created on: Mon Oct 17 17:16:31 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
syn/Release/conv_dyn_burst_ctrl_beh.prj deleted 100644 → 0
View file @ b4f182b5
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
syn/Release/conv_dyn_burst_ctrl_wave.fdo deleted 100644 → 0
View file @ b4f182b5
######################################################################
##
## Filename: conv_dyn_burst_ctrl_wave.fdo
## Created on: Mon Oct 17 17:16:32 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
syn/Release/conv_ttl_blo (2).xise deleted 100644 → 0
View file @ b4f182b5
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../top/Release/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../top/Release/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../sim/Release/testbenchv4.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../sim/Release/i2c_bus_model.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_burst_ctrl.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../sim/Release/burst_ctrl_tb.vhd" xil_pn:type="FILE_VHDL"/>
</files>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compiled Library Directory" xil_pn:value="C:/modeltech64_10.1c/win64" xil_pn:valueState="non-default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc7vx330t" xil_pn:valueState="default"/>
<property xil_pn:name="Device Family" xil_pn:value="Virtex7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/Release/conv_ttl_blo.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="vsim -version" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="ffg1157" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="5ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="5ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behav" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-11-19T11:12:54" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CD4A4EADF1EE50DFAAEFDC5B63F9C68F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
</project>
syn/Release/conv_ttl_blo.gise deleted 100644 → 0
View file @ b4f182b5
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
syn/Release/conv_ttl_blo.tcl deleted 100644 → 0
View file @ b4f182b5
#
# Project automation script for conv_ttl_blo
#
# Created for ISE version 14.7
#
# This file contains several Tcl procedures (procs) that you can use to automate
# your project by running from xtclsh or the Project Navigator Tcl console.
# If you load this file (using the Tcl command: source conv_ttl_blo.tcl), then you can
# run any of the procs included here.
#
# This script is generated assuming your project has HDL sources.
# Several of the defined procs won't apply to an EDIF or NGC based project.
# If that is the case, simply remove them from this script.
#
# You may also edit any of these procs to customize them. See comments in each
# proc for more instructions.
#
# This file contains the following procedures:
#
# Top Level procs (meant to be called directly by the user):
# run_process: you can use this top-level procedure to run any processes
# that you choose to by adding and removing comments, or by
# adding new entries.
# rebuild_project: you can alternatively use this top-level procedure
# to recreate your entire project, and the run selected processes.
#
# Lower Level (helper) procs (called under in various cases by the top level procs):
# show_help: print some basic information describing how this script works
# add_source_files: adds the listed source files to your project.
# set_project_props: sets the project properties that were in effect when this
# script was generated.
# create_libraries: creates and adds file to VHDL libraries that were defined when
# this script was generated.
# set_process_props: set the process properties as they were set for your project
# when this script was generated.
#
set myProject "conv_ttl_blo"
set myScript "conv_ttl_blo.tcl"
#
# Main (top-level) routines
#
# run_process
# This procedure is used to run processes on an existing project. You may comment or
# uncomment lines to control which processes are run. This routine is set up to run
# the Implement Design and Generate Programming File processes by default. This proc
# also sets process properties as specified in the "set_process_props" proc. Only
# those properties which have values different from their current settings in the project
# file will be modified in the project.
#
proc run_process {} {
global myScript
global myProject
## put out a 'heartbeat' - so we know something's happening.
puts "\n$myScript: running ($myProject)...\n"
if { ! [ open_project ] } {
return false
}
set_process_props
#
# Remove the comment characters (#'s) to enable the following commands
# process run "Synthesize"
# process run "Translate"
# process run "Map"
# process run "Place & Route"
#
set task "Implement Design"
if { ! [run_task $task] } {
puts "$myScript: $task run failed, check run output for details."
project close
return
}
set task "Generate Programming File"
if { ! [run_task $task] } {
puts "$myScript: $task run failed, check run output for details."
project close
return
}
puts "Run completed (successfully)."
project close
}
#
# rebuild_project
#
# This procedure renames the project file (if it exists) and recreates the project.
# It then sets project properties and adds project sources as specified by the
# set_project_props and add_source_files support procs. It recreates VHDL Libraries
# as they existed at the time this script was generated.
#
# It then calls run_process to set process properties and run selected processes.
#
proc rebuild_project {} {
global myScript
global myProject
project close
## put out a 'heartbeat' - so we know something's happening.
puts "\n$myScript: Rebuilding ($myProject)...\n"
set proj_exts [ list ise xise gise ]
foreach ext $proj_exts {
set proj_name "${myProject}.$ext"
if { [ file exists $proj_name ] } {
file delete $proj_name
}
}
project new $myProject
set_project_props
add_source_files
create_libraries
puts "$myScript: project rebuild completed."
run_process
}
#
# Support Routines
#
#
proc run_task { task } {
# helper proc for run_process
puts "Running '$task'"
set result [ process run "$task" ]
#
# check process status (and result)
set status [ process get $task status ]
if { ( ( $status != "up_to_date" ) && \
( $status != "warnings" ) ) || \
! $result } {
return false
}
return true
}
#
# show_help: print information to help users understand the options available when
# running this script.
#
proc show_help {} {
global myScript
puts ""
puts "usage: xtclsh $myScript <options>"
puts " or you can run xtclsh and then enter 'source $myScript'."
puts ""
puts "options:"
puts " run_process - set properties and run processes."
puts " rebuild_project - rebuild the project from scratch and run processes."
puts " set_project_props - set project properties (device, speed, etc.)"
puts " add_source_files - add source files"
puts " create_libraries - create vhdl libraries"
puts " set_process_props - set process property values"
puts " show_help - print this message"
puts ""
}
proc open_project {} {
global myScript
global myProject
if { ! [ file exists ${myProject}.xise ] } {
## project file isn't there, rebuild it.
puts "Project $myProject not found. Use project_rebuild to recreate it."
return false
}
project open $myProject
return true
}
#
# set_project_props
#
# This procedure sets the project properties as they were set in the project
# at the time this script was generated.
#
proc set_project_props {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: Setting project properties..."
project set family "Spartan6"
project set device "xc6slx45t"
project set package "fgg484"
project set speed "-3"
project set top_level_module_type "HDL"
project set synthesis_tool "XST (VHDL/Verilog)"
project set simulator "ISim (VHDL/Verilog)"
project set "Preferred Language" "Verilog"
project set "Enable Message Filtering" "false"
}
#
# add_source_files
#
# This procedure add the source files that were known to the project at the
# time this script was generated.
#
proc add_source_files {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: Adding sources to project..."
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_burst_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_regs.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
xfile add "../../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
xfile add "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
xfile add "../../sim/Release/burst_ctrl_tb.vhd"
xfile add "../../sim/Release/i2c_bus_model.vhd"
xfile add "../../sim/Release/testbenchv4.vhd"
xfile add "../../top/Release/conv_ttl_blo.ucf"
xfile add "../../top/Release/conv_ttl_blo.vhd"
# Set the Top Module as well...
project set top "arch" "conv_ttl_blo"
puts "$myScript: project sources reloaded."
} ; # end add_source_files
#
# create_libraries
#
# This procedure defines VHDL libraries and associates files with those libraries.
# It is expected to be used when recreating the project. Any libraries defined
# when this script was generated are recreated by this procedure.
#
proc create_libraries {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: Creating libraries..."
# must close the project or library definitions aren't saved.
project save
} ; # end create_libraries
#
# set_process_props
#
# This procedure sets properties as requested during script generation (either
# all of the properties, or only those modified from their defaults).
#
proc set_process_props {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: setting process properties..."
project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
project set "Global Optimization" "Off" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
project set "Place And Route Mode" "Route Only" -process "Place & Route"
project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
project set "Filter Files From Compile Order" "true"
project set "Last Applied Goal" "Balanced"
project set "Last Applied Strategy" "Xilinx Default (unlocked)"
project set "Last Unlock Status" "false"
project set "Manual Compile Order" "false"
project set "Placer Effort Level" "High" -process "Map"
project set "Extra Cost Tables" "0" -process "Map"
project set "LUT Combining" "Off" -process "Map"
project set "Combinatorial Logic Optimization" "false" -process "Map"
project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
project set "Power Reduction" "Off" -process "Map"
project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
project set "Project Description" ""
project set "Property Specification in Project File" "Store all values"
project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
project set "Case Implementation Style" "None" -process "Synthesize - XST"
project set "RAM Extraction" "true" -process "Synthesize - XST"
project set "ROM Extraction" "true" -process "Synthesize - XST"
project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
project set "Optimization Goal" "Speed" -process "Synthesize - XST"
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
project set "Resource Sharing" "true" -process "Synthesize - XST"
project set "Shift Register Extraction" "true" -process "Synthesize - XST"
project set "User Browsed Strategy Files" ""
project set "VHDL Source Analysis Standard" "VHDL-93"
project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
project set "Input TCL Command Script" "" -process "Generate Text Power Report"
project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Load Simulation File" "Default" -process "Generate Text Power Report"
project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Load Setting File" "" -process "Generate Text Power Report"
project set "Setting Output File" "" -process "Generate Text Power Report"
project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
project set "Essential Bits" "false" -process "Generate Programming File"
project set "Other Bitgen Command Line Options" "-g next_config_register_write:Disable" -process "Generate Programming File"
project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
project set "Show All Models" "false" -process "Generate IBIS Model"
project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
project set "Ignore User Timing Constraints" "false" -process "Map"
project set "Register Ordering" "4" -process "Map"
project set "Use RLOC Constraints" "Yes" -process "Map"
project set "Other Map Command Line Options" "" -process "Map"
project set "Use LOC Constraints" "true" -process "Translate"
project set "Other Ngdbuild Command Line Options" "" -process "Translate"
project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
project set "Ignore User Timing Constraints" "false" -process "Place & Route"
project set "Other Place & Route Command Line Options" "" -process "Place & Route"
project set "Use DSP Block" "Auto" -process "Synthesize - XST"
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
project set "Enable External Master Clock" "false" -process "Generate Programming File"
project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
project set "Create Bit File" "true" -process "Generate Programming File"
project set "Enable BitStream Compression" "false" -process "Generate Programming File"
project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
project set "Configuration Rate" "2" -process "Generate Programming File"
project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
project set "Watchdog Timer Value" "0x1FFF" -process "Generate Programming File"
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
project set "Drive Done Pin High" "false" -process "Generate Programming File"
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
project set "Maximum Compression" "false" -process "Map"
project set "Generate Detailed MAP Report" "true" -process "Map"
project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
project set "Perform Timing-Driven Packing and Placement" "false"
project set "Trim Unconnected Signals" "true" -process "Map"
project set "Create I/O Pads from Ports" "false" -process "Translate"
project set "Macro Search Path" "" -process "Translate"
project set "Netlist Translation Type" "Timestamp" -process "Translate"
project set "User Rules File for Netlister Launcher" "" -process "Translate"
project set "Allow Unexpanded Blocks" "false" -process "Translate"
project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing"
project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing"
project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
project set "Add I/O Buffers" "true" -process "Synthesize - XST"
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
project set "Keep Hierarchy" "No" -process "Synthesize - XST"
project set "Max Fanout" "100000" -process "Synthesize - XST"
project set "Register Balancing" "No" -process "Synthesize - XST"
project set "Register Duplication" "true" -process "Synthesize - XST"
project set "Library for Verilog Sources" "" -process "Synthesize - XST"
project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report"
project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
project set "Case" "Maintain" -process "Synthesize - XST"
project set "Cores Search Directories" "" -process "Synthesize - XST"
project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
project set "FSM Style" "LUT" -process "Synthesize - XST"
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
project set "Generics, Parameters" "" -process "Synthesize - XST"
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
project set "HDL INI File" "" -process "Synthesize - XST"
project set "LUT Combining" "Auto" -process "Synthesize - XST"
project set "Library Search Order" "" -process "Synthesize - XST"
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
project set "Power Reduction" "false" -process "Synthesize - XST"
project set "Read Cores" "true" -process "Synthesize - XST"
project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
project set "Verilog Include Directories" "" -process "Synthesize - XST"
project set "Verilog Macros" "" -process "Synthesize - XST"
project set "Work Directory" "C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release/xst" -process "Synthesize - XST"
project set "Write Timing Constraints" "false" -process "Synthesize - XST"
project set "Other XST Command Line Options" "" -process "Synthesize - XST"
project set "Timing Mode" "Performance Evaluation" -process "Map"
project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
project set "Generate Clock Region Report" "false" -process "Place & Route"
project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
project set "Power Reduction" "false" -process "Place & Route"
project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
project set "Auto Implementation Compile Order" "true"
project set "Equivalent Register Removal" "true" -process "Map"
project set "Placer Extra Effort" "None" -process "Map"
project set "Power Activity File" "" -process "Map"
project set "Register Duplication" "Off" -process "Map"
project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
project set "Synthesis Constraints File" "" -process "Synthesize - XST"
project set "RAM Style" "Auto" -process "Synthesize - XST"
project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
project set "Output File Name" "conv_ttl_blo" -process "Generate IBIS Model"
project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
project set "Create Binary Configuration File" "true" -process "Generate Programming File"
project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
project set "Create Logic Allocation File" "false" -process "Generate Programming File"
project set "Create Mask File" "false" -process "Generate Programming File"
project set "Retry Configuration if CRC Error Occurs" "true" -process "Generate Programming File"
project set "MultiBoot: Starting Address for Next Configuration" "0x0b170000" -process "Generate Programming File"
project set "MultiBoot: Starting Address for Golden Configuration" "0x0b000044" -process "Generate Programming File"
project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
project set "Enable Multi-Threading" "2" -process "Map"
project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
project set "ROM Style" "Auto" -process "Synthesize - XST"
project set "Safe Implementation" "No" -process "Synthesize - XST"
project set "Power Activity File" "" -process "Place & Route"
project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
project set "Encrypt Bitstream" "false" -process "Generate Programming File"
project set "Enable Multi-Threading" "Off" -process "Place & Route"
project set "AES Initial Vector" "" -process "Generate Programming File"
project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
project set "AES Key (Hex String)" "" -process "Generate Programming File"
project set "Input Encryption Key File" "" -process "Generate Programming File"
project set "Functional Model Target Language" "Verilog" -process "View HDL Source"
project set "Change Device Speed To" "-3" -process "Generate Post-Place & Route Static Timing"
project set "Change Device Speed To" "-3" -process "Generate Post-Map Static Timing"
puts "$myScript: project property values set."
} ; # end set_process_props
proc main {} {
if { [llength $::argv] == 0 } {
show_help
return true
}
foreach option $::argv {
switch $option {
"show_help" { show_help }
"run_process" { run_process }
"rebuild_project" { rebuild_project }
"set_project_props" { set_project_props }
"add_source_files" { add_source_files }
"create_libraries" { create_libraries }
"set_process_props" { set_process_props }
default { puts "unrecognized option: $option"; show_help }
}
}
}
if { $tcl_interactive } {
show_help
} else {
if {[catch {main} result]} {
puts "$myScript failed: $result."
}
}
syn/Release/conv_ttl_blo.xise deleted 100644 → 0
View file @ b4f182b5
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../sim/Release/burst_ctrl_tb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../sim/Release/i2c_bus_model.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/Release/testbenchv4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="130"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="130"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../top/Release/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/Release/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../sim/Release/fastevent_counter_tb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="chipscope_ila.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="chipscope_icon.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_blo|arch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/Release/conv_ttl_blo.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x0b000044" xil_pn:valueState="non-default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x0b170000" xil_pn:valueState="non-default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_blo" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_blo_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_blo_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_blo_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_blo_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="conv_ttl_blo" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="10ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0x1FFF" xil_pn:valueState="non-default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behav" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-02-07T16:30:27" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="64223241A98F4D938606EC70F10B22B0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
</project>
syn/Release/conv_ttl_blo_summary (2).html deleted 100644 → 0
View file @ b4f182b5
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>conv_ttl_blo Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc7vx330t-3ffg1157</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 10/19/2016 - 15:21:53</center>
</BODY></HTML>
\ No newline at end of file
syn/Release/conv_ttl_blo_tcl_v3.tcl deleted 100644 → 0
View file @ b4f182b5
#
# Project automation script for conv_ttl_blo
#
# Created for ISE version 14.7
#
# This file contains several Tcl procedures (procs) that you can use to automate
# your project by running from xtclsh or the Project Navigator Tcl console.
# If you load this file (using the Tcl command: source conv_ttl_blo.tcl), then you can
# run any of the procs included here.
#
# This script is generated assuming your project has HDL sources.
# Several of the defined procs won't apply to an EDIF or NGC based project.
# If that is the case, simply remove them from this script.
#
# You may also edit any of these procs to customize them. See comments in each
# proc for more instructions.
#
# This file contains the following procedures:
#
# Top Level procs (meant to be called directly by the user):
# run_process: you can use this top-level procedure to run any processes
# that you choose to by adding and removing comments, or by
# adding new entries.
# rebuild_project: you can alternatively use this top-level procedure
# to recreate your entire project, and the run selected processes.
#
# Lower Level (helper) procs (called under in various cases by the top level procs):
# show_help: print some basic information describing how this script works
# add_source_files: adds the listed source files to your project.
# set_project_props: sets the project properties that were in effect when this
# script was generated.
# create_libraries: creates and adds file to VHDL libraries that were defined when
# this script was generated.
# set_process_props: set the process properties as they were set for your project
# when this script was generated.
#
set myProject "conv_ttl_blo"
set myScript "conv_ttl_blo.tcl"
#
# Main (top-level) routines
#
# run_process
# This procedure is used to run processes on an existing project. You may comment or
# uncomment lines to control which processes are run. This routine is set up to run
# the Implement Design and Generate Programming File processes by default. This proc
# also sets process properties as specified in the "set_process_props" proc. Only
# those properties which have values different from their current settings in the project
# file will be modified in the project.
#
proc run_process {} {
global myScript
global myProject
## put out a 'heartbeat' - so we know something's happening.
puts "\n$myScript: running ($myProject)...\n"
if { ! [ open_project ] } {
return false
}
set_process_props
#
# Remove the comment characters (#'s) to enable the following commands
# process run "Synthesize"
# process run "Translate"
# process run "Map"
# process run "Place & Route"
#
set task "Implement Design"
if { ! [run_task $task] } {
puts "$myScript: $task run failed, check run output for details."
project close
return
}
set task "Generate Programming File"
if { ! [run_task $task] } {
puts "$myScript: $task run failed, check run output for details."
project close
return
}
puts "Run completed (successfully)."
project close
}
#
# rebuild_project
#
# This procedure renames the project file (if it exists) and recreates the project.
# It then sets project properties and adds project sources as specified by the
# set_project_props and add_source_files support procs. It recreates VHDL Libraries
# as they existed at the time this script was generated.
#
# It then calls run_process to set process properties and run selected processes.
#
proc rebuild_project {} {
global myScript
global myProject
project close
## put out a 'heartbeat' - so we know something's happening.
puts "\n$myScript: Rebuilding ($myProject)...\n"
set proj_exts [ list ise xise gise ]
foreach ext $proj_exts {
set proj_name "${myProject}.$ext"
if { [ file exists $proj_name ] } {
file delete $proj_name
}
}
project new $myProject
set_project_props
add_source_files
create_libraries
puts "$myScript: project rebuild completed."
run_process
}
#
# Support Routines
#
#
proc run_task { task } {
# helper proc for run_process
puts "Running '$task'"
set result [ process run "$task" ]
#
# check process status (and result)
set status [ process get $task status ]
if { ( ( $status != "up_to_date" ) && \
( $status != "warnings" ) ) || \
! $result } {
return false
}
return true
}
#
# show_help: print information to help users understand the options available when
# running this script.
#
proc show_help {} {
global myScript
puts ""
puts "usage: xtclsh $myScript <options>"
puts " or you can run xtclsh and then enter 'source $myScript'."
puts ""
puts "options:"
puts " run_process - set properties and run processes."
puts " rebuild_project - rebuild the project from scratch and run processes."
puts " set_project_props - set project properties (device, speed, etc.)"
puts " add_source_files - add source files"
puts " create_libraries - create vhdl libraries"
puts " set_process_props - set process property values"
puts " show_help - print this message"
puts ""
}
proc open_project {} {
global myScript
global myProject
if { ! [ file exists ${myProject}.xise ] } {
## project file isn't there, rebuild it.
puts "Project $myProject not found. Use project_rebuild to recreate it."
return false
}
project open $myProject
return true
}
#
# set_project_props
#
# This procedure sets the project properties as they were set in the project
# at the time this script was generated.
#
proc set_project_props {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: Setting project properties..."
project set family "Spartan6"
project set device "xc6slx45t"
project set package "fgg484"
project set speed "-3"
project set top_level_module_type "HDL"
project set synthesis_tool "XST (VHDL/Verilog)"
project set simulator "ISim (VHDL/Verilog)"
project set "Preferred Language" "Verilog"
project set "Enable Message Filtering" "false"
}
#
# add_source_files
#
# This procedure add the source files that were known to the project at the
# time this script was generated.
#
proc add_source_files {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: Adding sources to project..."
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_moving_average.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_regs.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
xfile add "../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
xfile add "../../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
xfile add "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
xfile add "../../top/Release/conv_ttl_blo.ucf"
xfile add "../../top/Release/conv_ttl_blo.vhd"
# Set the Top Module as well...
project set top "arch" "conv_ttl_blo"
puts "$myScript: project sources reloaded."
} ; # end add_source_files
#
# create_libraries
#
# This procedure defines VHDL libraries and associates files with those libraries.
# It is expected to be used when recreating the project. Any libraries defined
# when this script was generated are recreated by this procedure.
#
proc create_libraries {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: Creating libraries..."
# must close the project or library definitions aren't saved.
project save
} ; # end create_libraries
#
# set_process_props
#
# This procedure sets properties as requested during script generation (either
# all of the properties, or only those modified from their defaults).
#
proc set_process_props {} {
global myScript
if { ! [ open_project ] } {
return false
}
puts "$myScript: setting process properties..."
project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
project set "Global Optimization" "Off" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
project set "Place And Route Mode" "Route Only" -process "Place & Route"
project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
project set "Filter Files From Compile Order" "true"
project set "Last Applied Goal" "Balanced"
project set "Last Applied Strategy" "Xilinx Default (unlocked)"
project set "Last Unlock Status" "false"
project set "Manual Compile Order" "false"
project set "Placer Effort Level" "High" -process "Map"
project set "Extra Cost Tables" "0" -process "Map"
project set "LUT Combining" "Off" -process "Map"
project set "Combinatorial Logic Optimization" "false" -process "Map"
project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
project set "Power Reduction" "Off" -process "Map"
project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
project set "Project Description" ""
project set "Property Specification in Project File" "Store all values"
project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
project set "Case Implementation Style" "None" -process "Synthesize - XST"
project set "RAM Extraction" "true" -process "Synthesize - XST"
project set "ROM Extraction" "true" -process "Synthesize - XST"
project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
project set "Optimization Goal" "Speed" -process "Synthesize - XST"
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
project set "Resource Sharing" "true" -process "Synthesize - XST"
project set "Shift Register Extraction" "true" -process "Synthesize - XST"
project set "User Browsed Strategy Files" ""
project set "VHDL Source Analysis Standard" "VHDL-93"
project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
project set "Input TCL Command Script" "" -process "Generate Text Power Report"
project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Load Simulation File" "Default" -process "Generate Text Power Report"
project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Load Setting File" "" -process "Generate Text Power Report"
project set "Setting Output File" "" -process "Generate Text Power Report"
project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
project set "Essential Bits" "false" -process "Generate Programming File"
project set "Other Bitgen Command Line Options" "-g next_config_register_write:Disable" -process "Generate Programming File"
project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
project set "Show All Models" "false" -process "Generate IBIS Model"
project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
project set "Ignore User Timing Constraints" "false" -process "Map"
project set "Register Ordering" "4" -process "Map"
project set "Use RLOC Constraints" "Yes" -process "Map"
project set "Other Map Command Line Options" "" -process "Map"
project set "Use LOC Constraints" "true" -process "Translate"
project set "Other Ngdbuild Command Line Options" "" -process "Translate"
project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
project set "Ignore User Timing Constraints" "false" -process "Place & Route"
project set "Other Place & Route Command Line Options" "" -process "Place & Route"
project set "Use DSP Block" "Auto" -process "Synthesize - XST"
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
project set "Enable External Master Clock" "false" -process "Generate Programming File"
project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
project set "Create Bit File" "true" -process "Generate Programming File"
project set "Enable BitStream Compression" "false" -process "Generate Programming File"
project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
project set "Configuration Rate" "2" -process "Generate Programming File"
project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
project set "Watchdog Timer Value" "0x1FFF" -process "Generate Programming File"
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
project set "Drive Done Pin High" "false" -process "Generate Programming File"
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
project set "Maximum Compression" "false" -process "Map"
project set "Generate Detailed MAP Report" "true" -process "Map"
project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
project set "Perform Timing-Driven Packing and Placement" "false"
project set "Trim Unconnected Signals" "true" -process "Map"
project set "Create I/O Pads from Ports" "false" -process "Translate"
project set "Macro Search Path" "" -process "Translate"
project set "Netlist Translation Type" "Timestamp" -process "Translate"
project set "User Rules File for Netlister Launcher" "" -process "Translate"
project set "Allow Unexpanded Blocks" "false" -process "Translate"
project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing"
project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing"
project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
project set "Add I/O Buffers" "true" -process "Synthesize - XST"
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
project set "Keep Hierarchy" "No" -process "Synthesize - XST"
project set "Max Fanout" "100000" -process "Synthesize - XST"
project set "Register Balancing" "No" -process "Synthesize - XST"
project set "Register Duplication" "true" -process "Synthesize - XST"
project set "Library for Verilog Sources" "" -process "Synthesize - XST"
project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report"
project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
project set "Case" "Maintain" -process "Synthesize - XST"
project set "Cores Search Directories" "" -process "Synthesize - XST"
project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
project set "FSM Style" "LUT" -process "Synthesize - XST"
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
project set "Generics, Parameters" "" -process "Synthesize - XST"
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
project set "HDL INI File" "" -process "Synthesize - XST"
project set "LUT Combining" "Auto" -process "Synthesize - XST"
project set "Library Search Order" "" -process "Synthesize - XST"
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
project set "Power Reduction" "false" -process "Synthesize - XST"
project set "Read Cores" "true" -process "Synthesize - XST"
project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
project set "Verilog Include Directories" "" -process "Synthesize - XST"
project set "Verilog Macros" "" -process "Synthesize - XST"
project set "Work Directory" "C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release/xst" -process "Synthesize - XST"
project set "Write Timing Constraints" "false" -process "Synthesize - XST"
project set "Other XST Command Line Options" "" -process "Synthesize - XST"
project set "Timing Mode" "Performance Evaluation" -process "Map"
project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
project set "Generate Clock Region Report" "false" -process "Place & Route"
project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
project set "Power Reduction" "false" -process "Place & Route"
project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
project set "Auto Implementation Compile Order" "true"
project set "Equivalent Register Removal" "true" -process "Map"
project set "Placer Extra Effort" "None" -process "Map"
project set "Power Activity File" "" -process "Map"
project set "Register Duplication" "Off" -process "Map"
project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
project set "Synthesis Constraints File" "" -process "Synthesize - XST"
project set "RAM Style" "Auto" -process "Synthesize - XST"
project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
project set "Output File Name" "conv_ttl_blo" -process "Generate IBIS Model"
project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
project set "Create Binary Configuration File" "true" -process "Generate Programming File"
project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
project set "Create Logic Allocation File" "false" -process "Generate Programming File"
project set "Create Mask File" "false" -process "Generate Programming File"
project set "Retry Configuration if CRC Error Occurs" "true" -process "Generate Programming File"
project set "MultiBoot: Starting Address for Next Configuration" "0x0b170000" -process "Generate Programming File"
project set "MultiBoot: Starting Address for Golden Configuration" "0x0b000044" -process "Generate Programming File"
project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
project set "Enable Multi-Threading" "2" -process "Map"
project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
project set "ROM Style" "Auto" -process "Synthesize - XST"
project set "Safe Implementation" "No" -process "Synthesize - XST"
project set "Power Activity File" "" -process "Place & Route"
project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
project set "Encrypt Bitstream" "false" -process "Generate Programming File"
project set "Enable Multi-Threading" "Off" -process "Place & Route"
project set "AES Initial Vector" "" -process "Generate Programming File"
project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
project set "AES Key (Hex String)" "" -process "Generate Programming File"
project set "Input Encryption Key File" "" -process "Generate Programming File"
project set "Functional Model Target Language" "Verilog" -process "View HDL Source"
project set "Change Device Speed To" "-3" -process "Generate Post-Place & Route Static Timing"
project set "Change Device Speed To" "-3" -process "Generate Post-Map Static Timing"
puts "$myScript: project property values set."
} ; # end set_process_props
proc main {} {
if { [llength $::argv] == 0 } {
show_help
return true
}
foreach option $::argv {
switch $option {
"show_help" { show_help }
"run_process" { run_process }
"rebuild_project" { rebuild_project }
"set_project_props" { set_project_props }
"add_source_files" { add_source_files }
"create_libraries" { create_libraries }
"set_process_props" { set_process_props }
default { puts "unrecognized option: $option"; show_help }
}
}
}
if { $tcl_interactive } {
show_help
} else {
if {[catch {main} result]} {
puts "$myScript failed: $result."
}
}
syn/Release/fuse.xmsgs deleted 100644 → 0
View file @ b4f182b5
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
syn/Release/fuseRelaunch.cmd deleted 100644 → 0
View file @ b4f182b5
-intstyle "ise" -incremental -rangecheck -lib "secureip" -o "C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/testbench_isim_beh.exe" -prj "C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/testbench_beh.prj" "work.testbench"
syn/Release/iseconfig/conv_ttl_blo.projectmgr deleted 100644 → 0
View file @ b4f182b5
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="conv_ttl_blo" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="ManualCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/Automatic `includes</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\top\conv_common_gw_pkg.vhd (C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000004c7000000020000000000000000000000000200000064ffffffff000000810000000300000002000004570000000100000003000000700000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\ip_cores\conv-common-gw\top\conv_common_gw_pkg.vhd (C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001af000000010000000100000000000000000000000064ffffffff000000810000000000000001000001af0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >96</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000052f000000040101000100000000000000000000000064ffffffff000000810000000000000004000003c800000001000000000000009d0000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001af000000010000000100000000000000000000000064ffffffff000000810000000000000001000001af0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/Automatic `includes</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_i2c_bridge - wb_i2c_bridge - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_multiboot - xwb_xil_multiboot - struct</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_pulse_timetag - conv_pulse_timetag - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_i2c_bridge - wb_i2c_bridge - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_multiboot - xwb_xil_multiboot - struct</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_onewire_master - wb_onewire_master - rtl</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_pulse_timetag - conv_pulse_timetag - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>conv_ttl_blo</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000005b7000000020000000000000000000000000200000064ffffffff000000810000000300000002000005b70000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>conv_ttl_blo</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/Automatic `includes</ClosedNode>
<ClosedNode>/conv_common_gw - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|top|conv_common_gw.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_multiboot - xwb_xil_multiboot - struct</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_pulse_timetag - conv_pulse_timetag - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_i2c_bridge - wb_i2c_bridge - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_multiboot - xwb_xil_multiboot - struct</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_pulse_timetag - conv_pulse_timetag - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/conv_ttl_blo - arch G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|top|Release|conv_ttl_blo.vhd/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_frequency_meter - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_frequency_meter.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_moving_average - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_moving_average.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/gc_rr_arbiter - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|common|gc_rr_arbiter.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/generic_shiftreg_fifo - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|genrams|generic|generic_shiftreg_fifo.vhd</ClosedNode>
<ClosedNode>/testbench - behav C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch</ClosedNode>
<ClosedNode>/testbench - behav C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_master - i2c_master_byte_ctrl - structural</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_i2c_bridge - wb_i2c_bridge - behav</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_multiboot - xwb_xil_multiboot - struct</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_onewire_master - wb_onewire_master - rtl</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_pulse_timetag - conv_pulse_timetag - behav</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_ring_buf - conv_ring_buf - behav</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_dut - conv_ttl_blo - arch/cmp_conv_common - conv_common_gw - arch/cmp_wb_crossbar - xwb_sdb_crossbar - rtl</ClosedNode>
<ClosedNode>/testbench - behav G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|sim|Release|testbenchv4.vhd/cmp_master - i2c_master_byte_ctrl - structural</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_lm32 - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_lm32.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_master - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_master.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_irq_timer - behavioral G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_irq|wb_irq_timer.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_serial_lcd - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_serial_lcd|wb_serial_lcd.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wb_spi_flash - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi_flash|wb_spi_flash.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_dpssram - syn G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_dpssram.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/wbgen2_fifo_async - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wbgen2|wbgen2_fifo_async.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_async_bridge - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_async_bridge|xwb_async_bridge.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_bus_fanout - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_bus_fanout|xwb_bus_fanout.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_dpram - struct G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dpram|xwb_dpram.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_gpio_port - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_gpio_port|xwb_gpio_port.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_i2c_master - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_i2c_master|xwb_i2c_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_onewire_master - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_onewire_master|xwb_onewire_master.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_pwm - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_pwm|xwb_simple_pwm.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_simple_uart - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_uart|xwb_simple_uart.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_spi - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_spi|xwb_spi.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_streamer - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_dma|xwb_streamer.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_tics - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_simple_timer|xwb_tics.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_vic - wrapper G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|modules|wishbone|wb_vic|xwb_vic.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl C:|Users|debouhir|work|CONV-TTL-BLO|conv-ttl-blo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
<ClosedNode>/xwb_xilinx_fpga_loader - rtl G:|Users|d|debouhir|Documents|Projects|CONV-TTL-BlO|repo|conv-ttl-blo-gw|ip_cores|conv-common-gw|ip_cores|general-cores|platform|xilinx|wb_xilinx_fpga_loader|xwb_xilinx_fpga_loader.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>conv_ttl_blo</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000502000000020000000000000000000000000200000064ffffffff000000810000000300000002000005020000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>conv_ttl_blo</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001af000000010000000100000000000000000000000064ffffffff000000810000000000000001000001af0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>ModelSim Simulator</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001af000000010000000100000000000000000000000064ffffffff000000810000000000000001000001af0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>ModelSim Simulator</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001af000000010000000100000000000000000000000064ffffffff000000810000000000000001000001af0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000014d000000de01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>ISim Simulator</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="PostTransSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/testbench - behav C:|Users|debouhir|work|CONV-TTL-BLO|repo|conv-ttl-blo-gw|sim|Release|burst_ctrl_tb.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Unassigned User Library Modules</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000029f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000029f0000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Unassigned User Library Modules</CurrentItem>
</ItemView>
<ItemView engineview="PostTransSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000040c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000040c0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="PostMapSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000029f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000029f0000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>cmp_dut_1 - conv_burst_ctrl</CurrentItem>
</ItemView>
<ItemView engineview="PostMapSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Design Utilities</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001af000000010000000100000000000000000000000064ffffffff000000810000000000000001000001af0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Design Utilities</CurrentItem>
</ItemView>
<ItemView engineview="PostMapSim" guiview="Source" compilemode="ManualCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>C:\Users\debouhir\work\CONV-TTL-BLO\repo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd (C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/sim/Release/burst_ctrl_tb.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000020000000000000000000000000000000064ffffffff0000008100000000000000020000024a0000000100000000000000700000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>C:\Users\debouhir\work\CONV-TTL-BLO\repo\conv-ttl-blo-gw\sim\Release\burst_ctrl_tb.vhd (C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/sim/Release/burst_ctrl_tb.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="PostMapSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Simulate Post-Map Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000040c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000040c0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Post-Map Model</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000032e000000010000000100000000000000000000000064ffffffff0000008100000000000000010000032e0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
</Project>
syn/Release/iseconfig/conv_ttl_blo.xreport deleted 100644 → 0
View file @ b4f182b5
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2017-03-07T13:10:09</DateModified>
<ModuleName>conv_ttl_blo</ModuleName>
<SummaryTimeStamp>2017-03-07T09:41:56</SummaryTimeStamp>
<ImplementationReportsDirectory>C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\</ImplementationReportsDirectory>
<DateInitialized>2017-02-10T11:32:52</DateInitialized>
<SavedFilePath>C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release/iseconfig/conv_ttl_blo.xreport</SavedFilePath>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="conv_ttl_blo_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="conv_ttl_blo_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="conv_ttl_blo_map.xrpt" showConstraints="0" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="conv_ttl_blo_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="conv_ttl_blo_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="conv_ttl_blo.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="conv_ttl_blo_par.xrpt" showConstraints="0" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="conv_ttl_blo_par.xrpt" showConstraints="0" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="conv_ttl_blo.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="conv_ttl_blo_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="conv_ttl_blo_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="conv_ttl_blo.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="conv_ttl_blo.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="conv_ttl_blo.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="conv_ttl_blo.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/conv_ttl_blo_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/conv_ttl_blo_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="conv_ttl_blo_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/conv_ttl_blo_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="conv_ttl_blo_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="conv_ttl_blo.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/conv_ttl_blo_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/conv_ttl_blo_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
syn/Release/iseconfig/testbench.xreport deleted 100644 → 0
View file @ b4f182b5
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2016-10-24T10:13:11</DateModified>
<ModuleName>conv_ttl_blo</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/iseconfig/testbench.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release</ImplementationReportsDirectory>
<DateInitialized>2016-10-24T10:13:11</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="conv_ttl_blo_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="conv_ttl_blo_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="conv_ttl_blo_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="conv_ttl_blo_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="conv_ttl_blo_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="conv_ttl_blo.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="conv_ttl_blo_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="conv_ttl_blo_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="conv_ttl_blo.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="conv_ttl_blo_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="conv_ttl_blo_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="conv_ttl_blo.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="conv_ttl_blo.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="conv_ttl_blo.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="conv_ttl_blo.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="conv_ttl_blo.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="conv_ttl_blo.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/conv_ttl_blo_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/conv_ttl_blo_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="conv_ttl_blo_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/conv_ttl_blo_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="conv_ttl_blo_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="conv_ttl_blo.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/conv_ttl_blo_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="conv_ttl_blo.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/conv_ttl_blo_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
syn/Release/modelsim.ini deleted 100644 → 0
View file @ b4f182b5
; Copyright 1991-2012 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
others = $MODEL_TECH/../modelsim.ini
;
; VITAL concerns:
;
; The library ieee contains (among other packages) the packages of the
; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
; the physical library ieee (recommended), or use the physical library
; vital2000, but not both. The design can use logical library ieee and/or
; vital2000 as long as each of these maps to the same physical library, either
; ieee or vital2000.
;
; A design using the 1995 version of the VITAL packages, whether or not
; it also uses the 2000 version of the VITAL packages, must have logical library
; name ieee mapped to physical library vital1995. (A design cannot use library
; vital1995 directly because some packages in this library use logical name ieee
; when referring to the other packages in the library.) The design source
; should use logical name ieee when referring to any packages there except the
; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
; name vital2000 (mapped to physical library vital2000) to refer to those
; packages.
; ieee = $MODEL_TECH/../vital1995
;
; For compatiblity with previous releases, logical library name vital2000 maps
; to library vital2000 (a different library than library ieee, containing the
; same packages).
; A design should not reference VITAL from both the ieee library and the
; vital2000 library because the vital packages are effectively different.
; A design that references both the ieee and vital2000 libraries must have
; both logical names ieee and vital2000 mapped to the same library, either of
; these:
; $MODEL_TECH/../ieee
; $MODEL_TECH/../vital2000
;
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib
secureip = C:\modeltech64_10.1c\win64/secureip
unisim = C:\modeltech64_10.1c\win64/unisim
unimacro = C:\modeltech64_10.1c\win64/unimacro
unisims_ver = C:\modeltech64_10.1c\win64/unisims_ver
unimacro_ver = C:\modeltech64_10.1c\win64/unimacro_ver
simprim = C:\modeltech64_10.1c\win64/simprim
simprims_ver = C:\modeltech64_10.1c\win64/simprims_ver
xilinxcorelib = C:\modeltech64_10.1c\win64/xilinxcorelib
xilinxcorelib_ver = C:\modeltech64_10.1c\win64/xilinxcorelib_ver
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Value of 3 or 2008 for VHDL-2008
VHDL93 = 2002
; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
; ignoreStandardRealVector = 1
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Turns on lint-style checking.
; Show_Lint = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
; Run the 0-in compiler on the VHDL source files
; Default is off.
; ZeroIn = 1
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
; Set the prefix to be honored for synthesis/coverage pragma recognition.
; Default is "".
; AddPragmaPrefix = ""
; Ignore synthesis and coverage pragmas with this prefix.
; Default is "".
; IgnorePragmaPrefix = ""
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverSub = 0
; Automatically exclude VHDL case statement OTHERS choice branches.
; This includes OTHERS choices in selected signal assigment statements.
; Default is to not exclude.
; CoverExcludeDefault = 1
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
; Turn on or off clkOpt optimization for code coverage. Default is on.
; CoverClkOpt = 1
; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
; CoverClkOptBuiltins = 0
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
; Increase or decrease the maximum number of rows allowed in a FEC table, implementing
; a condition coverage or expression coverage expression, by changing FecEffort.
; Higher FecEffort leads to a longer compile time, but more expressions covered.
; This is a number from 1 to 3, with the following meanings (the default is 1):
; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.
; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.
; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.
; FecEffort = 2
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0
; Enable or disable UDP Coverage analysis for conditions and expressions.
; UDP Coverage data is disabled by default when expression and/or condition
; coverage is active.
; CoverUDP = 1
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
; Set this to cause the compilers to force data to be committed to disk
; when the files are closed.
; SyncCompilerFiles = 1
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0
; Turn ON detection of FSMs having single bit current state variable.
; FsmSingle = 1
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
; Turn ON detection of FSM Implicit Transitions.
; FsmImplicitTrans = 1
; Controls whether or not to show immediate assertions with constant expressions
; in GUI/report/UCDB etc. By default, immediate assertions with constant
; expressions are shown in GUI/report/UCDB etc. This does not affect
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0
; Controls how VHDL basic identifiers are stored with the design unit.
; Does not make the language case-sensitive, affects only how declarations
; declared with basic identifiers have their names stored and printed
; (in the GUI, examine, etc.).
; Default is to preserve the case as originally depicted in the VHDL source.
; Value of 0 indicates to change all basic identifiers to lower case.
; PreserveCase = 0
; For Configuration Declarations, controls the effect that USE clauses have
; on visibility inside the configuration items being configured. If 1
; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
; extend the visibility of objects made visible through USE clauses into nested
; component configurations.
; OldVHDLConfigurationVisibility = 0
; Allows VHDL configuration declarations to be in a different library from
; the corresponding configured entity. Default is to not allow this for
; stricter LRM-compliance.
; SeparateConfigLibrary = 1;
; Determine how mode OUT subprogram parameters of type array and record are treated.
; If 0 (the default), then only VHDL 2008 will do this initialization.
; If 1, always initialize the mode OUT parameter to its default value.
; If 2, do not initialize the mode OUT out parameter.
; Note that prior to release 10.1, all language versions did not initialize mode
; OUT array and record type parameters, unless overridden here via this mechanism.
; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
; initialization, unless overridden here.
; InitOutCompositeParam = 0
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Turns on lint-style checking.
; Show_Lint = 1
; Show source line containing error. Default is off.
; Show_source = 1
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with depth equal
; to or greater than 1M are marked as sparse)
; SparseMemThreshold = 1048576
; Run the 0-in compiler on the Verilog source files
; Default is off.
; ZeroIn = 1
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
; Set the prefix to be honored for synthesis and coverage pragma recognition.
; Default is "".
; AddPragmaPrefix = ""
; Ignore synthesis and coverage pragmas with this prefix.
; Default is "".
; IgnorePragmaPrefix = ""
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
; Automatically exclude Verilog case statement default branches.
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1
; Increase or decrease the maximum number of rows allowed in a FEC table, implementing
; a condition coverage or expression coverage expression, by changing FecEffort.
; Higher FecEffort leads to a longer compile time, but more expressions covered.
; This is a number from 1 to 3, with the following meanings (the default is 1):
; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.
; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.
; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.
; FecEffort = 2
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverFEC = 0
; Enable or disable UDP Coverage analysis for conditions and expressions.
; UDP Coverage data is disabled by default when expression and/or condition
; coverage is active.
; CoverUDP = 1
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverShortCircuit = 0
; Turn on code coverage in VLOG `celldefine modules, modules containing
; specify blocks, and modules included using vlog -v and -y. Default is off.
; CoverCells = 1
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 0 to 5, with the following
; meanings (the default is 3):
; 5 -- All allowable optimizations are on.
; 4 -- Turn off removing unreferenced code.
; 3 -- Turn off process, always block and if statement merging.
; 2 -- Turn off expression optimization, converting primitives
; to continuous assignments, VHDL subprogram inlining.
; and VHDL clkOpt (converting FF's to builtins).
; 1 -- Turn off continuous assignment optimizations and clock suppression.
; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
; level 3, with also turning off converting primitives to continuous assigns.
; CoverOpt = 3
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; in the [vsim] section can override this value.
; SVCovergroupGoalDefault = 100
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; in the [vsim] section can override this value.
; SVCovergroupTypeGoalDefault = 100
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
; SVCovergroupStrobeDefault = 0
; Specify the override for the default value of "merge_instances" option for
; the Covergroup Type. This is a compile time option which forces
; "merge_instances" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupMergeInstancesDefault = 0
; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero).
; SVCovergroupPerInstanceDefault = 0
; Specify the override for the default value of "get_inst_coverage" option for the
; Covergroup variables. This is a compile time option which forces
; "get_inst_coverage" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupGetInstCoverageDefault = 0
;
; A space separated list of resource libraries that contain precompiled
; packages. The behavior is identical to using the "-L" switch.
;
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
; The behavior is identical to the "-mixedansiports" switch. Default is off.
; MixedAnsiPorts = 1
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1
; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1
; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5
; Turn ON detection of FSMs having single bit current state variable.
; FsmSingle = 1
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
; Turn off detections of FSMs having x-assignment.
; FsmXAssign = 0
; Turn ON detection of FSM Implicit Transitions.
; FsmImplicitTrans = 1
; List of file suffixes which will be read as SystemVerilog. White space
; in extensions can be specified with a back-slash: "\ ". Back-slashes
; can be specified with two consecutive back-slashes: "\\";
; SVFileExtensions = sv svp svh
; This setting is the same as the vlog -sv command line switch.
; Enables SystemVerilog features and keywords when true (1).
; When false (0), the rules of IEEE Std 1364-2001 are followed and
; SystemVerilog keywords are ignored.
; Svlog = 0
; Prints attribute placed upon SV packages during package import
; when true (1). The attribute will be ignored when this
; entry is false (0). The attribute name is "package_load_message".
; The value of this attribute is a string literal.
; Default is true (1).
; PrintSVPackageLoadingAttribute = 1
; Do not show immediate assertions with constant expressions in
; GUI/reports/UCDB etc. By default immediate assertions with constant
; expressions are shown in GUI/reports/UCDB etc. This does not affect
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0
; Controls if untyped parameters that are initialized with values greater
; than 2147483647 are mapped to generics of type INTEGER or ignored.
; If mapped to VHDL Integers, values greater than 2147483647
; are mapped to negative values.
; Default is to map these parameter to generic of type INTEGER
; ForceUnsignedToVHDLInteger = 1
; Enable AMS wreal (wired real) extensions. Default is 0.
; WrealType = 1
; Controls SystemVerilog Language Extensions. These options enable
; some non-LRM compliant behavior. Valid extensions are "feci",
; "pae", "uslt" and "spsl".
; SVExtensions = uslt,spsl
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g
; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++
; Enable verbose messages from sccom. Default is off.
; SccomVerbose = 1
; sccom logfile. Default is no logfile.
; SccomLogfile = sccom.log
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft
; Control compiler optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
; Increase or decrease the maximum number of rows allowed in a FEC table, implementing
; a condition coverage or expression coverage expression, by changing FecEffort.
; Higher FecEffort leads to a longer compile time, but more expressions covered.
; This is a number from 1 to 3, with the following meanings (the default is 1):
; 3 -- High FecEffort, Allows large expressions to be covered, will cause longer compile time.
; 2 -- Medium FecEffort, Allows more number of inputs per expression than Low FecEffort to be covered.
; 1 -- Low FecEffort, Covers only small expressions or conditions and skips larger ones.
; FecEffort = 2
; Enable code coverage reporting of code that has been optimized away.
; The default is not to report.
; CoverReportCancelled = 1
; Do not show immediate assertions with constant expressions in
; GUI/reports/UCDB etc. By default immediate assertions with constant
; expressions are shown in GUI/reports/UCDB etc. This does not affect
; evaluation of immediate assertions.
; ShowConstantImmediateAsserts = 0
; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000
; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200
; Set the number of processes created during the code generation phase.
; By default a heuristic is used to set this value. This may be set to 0
; to disable this feature completely.
; ParallelJobs = 0
; Controls SystemVerilog Language Extensions. These options enable
; some non-LRM compliant behavior. Valid extensions are "feci",
; "pae", "uslt" and "spsl".
; SVExtensions = uslt,spsl
[vsim]
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; Disable certain code coverage exclusions automatically.
; Assertions and FSM are exluded from the code coverage by default
; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
; Or specify comma or space separated list
;AutoExclusionsDisable = fsm,assertions
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1
; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
; -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1
; Control SVA and VHDL immediate assertion directives during simulation
; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
; SimulateImmedAsserts = 1
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; noviewer Disable checkout of msimviewer and vsim-viewer license
; features (PE ONLY)
; noslvhdl Disable checkout of qhsimvh and vsim license features
; noslvlog Disable checkout of qhsimvl and vsimvlog license features
; nomix Disable checkout of msimhdlmix and hdlmix license features
; nolnl Disable checkout of msimhdlsim and hdlsim license features
; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
; features
; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
; hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus
; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
; which will cause a running simulation to stop.
; VHDL assertions and SystemVerilog immediate assertions that occur with the
; given severity or higher will cause a running simulation to stop.
; This value is ignored during elaboration.
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; The class debug feature enables more visibility and tracking of class instances
; during simulation. By default this feature is 0 (disabled). To enable this
; feature set ClassDebug to 1.
; ClassDebug = 1
; Message Format conversion specifications:
; %S - Severity Level of message/assertion
; %R - Text of message
; %T - Time of message
; %D - Delta value (iteration number) of Time
; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
; %i - Instance/Region/Signal pathname with Process name (if available)
; %I - shorthand for one of these:
; " %K: %i"
; " %K: %i File: %F" (when path is not Process or Signal)
; except that the %i in this case does not report the Process name
; %O - Process name
; %P - Instance/Region path without leaf process
; %F - File name
; %L - Line number; if assertion message, then line number of assertion or, if
; assertion is in a subprogram, line from which the call is made
; %u - Design unit name in form library.primary
; %U - Design unit name in form library.primary(secondary)
; %% - The '%' character itself
;
; If specific format for Severity Level is defined, use that format.
; Else, for a message that occurs during elaboration:
; -- Failure/Fatal message in VHDL region that is not a Process, and in
; certain non-VHDL regions, uses MessageFormatBreakLine;
; -- Failure/Fatal message otherwise uses MessageFormatBreak;
; -- Note/Warning/Error message uses MessageFormat.
; Else, for a message that occurs during runtime and triggers a breakpoint because
; of the BreakOnAssertion setting:
; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
; -- otherwise uses MessageFormatBreak.
; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
;
; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Error File - alternate file for storing error messages
; ErrorFile = error.log
; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops because of a breakpoint or fatal error.
; Example with function name: # Break in Process ctr at counter.vhd line 44
; Example without function name: # Break at counter.vhd line 44
; Default value is 1.
ShowFunctions = 1
; Default radix for all windows and commands.
; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
; Flags may be one of: enumnumeric, showbase
DefaultRadix = symbolic
;DefaultRadixFlags = showbase
; VSIM Startup command
; Startup = do startup.do
; VSIM Shutdown file
; Filename to save u/i formats and configurations.
; ShutdownFile = restart.do
; To explicitly disable auto save:
; ShutdownFile = --disable-auto-save
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Specify a unique path separator for the Signal Spy set of functions.
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /
; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.
; If set to 0, the syntax of the source language must be used.
; Each identifier in a hierarchical name may need different syntax,
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
; GenerousIdentifierParsing = 1
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Disable SystemVerilog assertion messages
; IgnoreSVAInfo = 1
; IgnoreSVAWarning = 1
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
; Do not print any additional information from Severity System tasks.
; Only the message provided by the user is printed along with severity
; information.
; SVAPrintOnlyUserMessage = 1;
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; Control the iteration of events when a VHDL signal is forced to a value
; This flag can be set to honour the signal update event in next iteration,
; the default is to update and propagate in the same iteration.
; ForceSigNextIter = 1
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0
; Turn off warnings from accelerated versions of the std_logic_arith,
; std_logic_unsigned, and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from accelerated versions of the IEEE numeric_std
; and numeric_bit packages.
NumericStdNoWarnings = 1
; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
; in the design hierarchy.
; This style is controlled by the value of the GenerateFormat
; value described next. Default is to use new-style names, which
; comprise the generate statement label, '(', the value of the generate
; parameter, and a closing ')'.
; Uncomment this to use old-style names.
; OldVhdlForGenNames = 1
; Control the format of the old-style VHDL FOR generate statement region
; name for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate statement label; the %d represents the generate parameter value
; at a particular iteration (this is the position number if the generate parameter
; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
; leading and trailing whitespace is ignored.
; Application of the format must result in a unique region name over all
; loop iterations for a particular immediately enclosing scope so that name
; lookup can function properly. The default is %s__%d.
; GenerateFormat = %s__%d
; Enable changes in VHDL elaboration to allow for Variable Logging
; This trades off simulation performance for the ability to log variables
; efficiently. By default this is disable for maximum simulation performance
; VhdlVariableLogging = 1
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
; Use custom gcc compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; DpiCppPath = <your-gcc-installation>/bin/gcc
; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
; The term "out-of-the-blue" refers to SystemVerilog export function calls
; made from C functions that don't have the proper context setup
; (as is the case when running under "DPI-C" import functions).
; When this is enabled, one can call a DPI export function
; (but not task) from any C code.
; the setting of this variable can be one of the following values:
; 0 : dpioutoftheblue call is disabled (default)
; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
; DpiOutOfTheBlue = 1
; Specify whether continuous assignments are run before other normal priority
; processes scheduled in the same iteration. This event ordering minimizes race
; differences between optimized and non-optimized designs, and is the default
; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
; ImmediateContinuousAssign to 0.
; The default is 1 (enabled).
; ImmediateContinuousAssign = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Which default VPI object model should the tool conform to?
; The 1364 modes are Verilog-only, for backwards compatibility with older
; libraries, and SystemVerilog objects are not available in these modes.
;
; In the absence of a user-specified default, the tool default is the
; latest available LRM behavior.
; Options for PliCompatDefault are:
; VPI_COMPATIBILITY_VERSION_1364v1995
; VPI_COMPATIBILITY_VERSION_1364v2001
; VPI_COMPATIBILITY_VERSION_1364v2005
; VPI_COMPATIBILITY_VERSION_1800v2005
; VPI_COMPATIBILITY_VERSION_1800v2008
;
; Synonyms for each string are also recognized:
; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
; Specify whether the Verilog system task $fopen or vpi_mcd_open()
; will create directories that do not exist when opening the file
; in "a" or "w" mode.
; The default is 0 (do not create non-existent directories)
; CreateDirForFileAccess = 1
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; DefaultRestartOptions = -force
; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe.
; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
; The list of options must be delimited by commas, without spaces or tabs.
; The default is UVMControl = struct
; Some examples
; To turn on all available UVM-aware debug features:
; UVMControl = all
; To turn on the struct window, mesage logging, and transaction logging:
; UVMControl = struct,msglog,trlog
; To turn on all options except certe:
; UVMControl = all,-certe
; To completely disable all UVM-aware debug functionality:
; UVMControl = disable
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Specify whether or not a WLF file should be optimized during
; simulation. If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0
; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf
; Specify whether to lock the WLF file.
; Locking the file prevents other invocations of ModelSim/Questa tools from
; inadvertently overwriting the WLF file.
; The default is 1, lock the WLF file.
; WLFFileLock = 0
; Specify the update interval for the WLF file.
; Value is the number of seconds between updated. After at least the
; interval number of seconds, the wlf file is flushed, ensuring that the data
; is correct when viewed from a separate live viewer. Setting to 0 means no
; updating. Default is 10 seconds, which has a tiny performance impact
; WLFUpdateInterval = 10
; Specify the WLF reader cache size limit for each open WLF file.
; The size is giving in megabytes. A value of 0 turns off the
; WLF cache.
; WLFSimCacheSize allows a different cache size to be set for
; simulation WLF file independent of post-simulation WLF file
; viewing. If WLFSimCacheSize is not set it defaults to the
; WLFCacheSize setting.
; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most
; platforms; on Windows, the setting is 1000M to help avoid filling process memory.
; WLFCacheSize = 2000
; WLFSimCacheSize = 500
; Specify the WLF file event collapse mode.
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
; 1 = Only record values of logged objects at the end of a simulator iteration.
; (same as -wlfcollapsedelta)
; 2 = Only record values of logged objects at the end of a simulator time step.
; (same as -wlfcollapsetime)
; The default is 1.
; WLFCollapseMode = 0
; Specify whether WLF file logging can use threads on multi-processor machines
; if 0, no threads will be used, if 1, threads will be used if the system has
; more than one processor
; WLFUseThreads = 1
; Specify the relative size of logged objects that will trigger "large object"
; messages at log/wave/list time. This size value is an approximation of
; the number of bytes needed to store the value of the object before compression
; and optimization.
; The default LargeObjectSize size is 500k
; LargeObjectSize = 500000
; Specify whether to output "large object" warning messages.
; The default is 0 which means the warning messages will come out.
; LargeObjectSilent = 0
; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0
; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
; ScShowIeeeDeprecationWarnings = 1
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
; ScEnableScSignalWriteCheck = 1
; Set SystemC default time unit.
; Set to fs, ps, ns, us, ms, or sec with optional
; prefix of 1, 10, or 100. The default is 1 ns.
; The ScTimeUnit value is honored if it is coarser than Resolution.
; If ScTimeUnit is finer than Resolution, it is set to the value
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
; then the default time unit will be 1 ns. However if Resolution
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
ScTimeUnit = ns
; Set SystemC sc_main stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
; on the amount of data on the sc_main() stack and the memory required
; to succesfully execute the longest function call chain of sc_main().
ScMainStackSize = 10 Mb
; Turn on/off execution of remainder of sc_main upon quitting the current
; simulation session. If the cumulative length of sc_main() in terms of
; simulation time units is less than the length of the current simulation
; run upon quit or restart, sc_main() will be in the middle of execution.
; This switch gives the option to execute the remainder of sc_main upon
; quitting simulation. The drawback of not running sc_main till the end
; is memory leaks for objects created by sc_main. If on, the remainder of
; sc_main will be executed ignoring all delays. This may cause the simulator
; to crash if the code in sc_main is dependent on some simulation state.
; Default is on.
ScMainFinishOnQuit = 1
; Set the SCV relationship name that will be used to identify phase
; relations. If the name given to a transactor relation matches this
; name, the transactions involved will be treated as phase transactions
ScvPhaseRelationName = mti_phase
; Customize the vsim kernel shutdown behavior at the end of the simulation.
; Some common causes of the end of simulation are $finish (implicit or explicit),
; sc_stop(), tf_dofinish(), and assertion failures.
; This should be set to "ask", "exit", or "stop". The default is "ask".
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
; In GUI mode, a dialog box will pop up and ask for user confirmation
; whether or not to quit the simulation.
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
; post-simulation tasks easier.
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
; "final" -- Run SystemVerilog final blocks then behave as "stop".
; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
OnFinish = ask
; Print pending deferred assertion messages.
; Deferred assertion messages may be scheduled after the $finish in the same
; time step. Deferred assertions scheduled to print after the $finish are
; printed before exiting with severity level NOTE since it's not known whether
; the assertion is still valid due to being printed in the active region
; instead of the reactive region where they are normally printed.
; OnFinishPendingAssert = 1;
; Print "simstats" result
; 0 == do not print simstats
; 1 == print at end of simulation
; 2 == print at end of run
; 3 == print at end of run and end of simulation
; default == 0
; PrintSimStats = 1
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log
; Enable assertion counts. Default is off.
; AssertionCover = 1
; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1
; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
; AssertionEnable = 0
; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionLimit = 1
; Turn on/off concurrent assertion pass log. Default is off.
; Assertion pass logging is only enabled when assertion is browseable
; and assertion debug is enabled.
; AssertionPassLog = 1
; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0
; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
; AssertionFailLocalVarLog = 0
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue 1 = Break 2 = Exit
; AssertionFailAction = 1
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1
; Control how many waveform rows will be used for displaying the active threads. Default is 5.
; AssertionActiveThreadMonitorLimit = 5
; Assertion thread limit after which assertion would be killed/switched off.
; The default is -1 (unlimited). If the number of threads for an assertion go
; beyond this limit, the assertion would be either switched off or killed. This
; limit applies to only assert directives.
;AssertionThreadLimit = -1
; Action to be taken once the assertion thread limit is reached. Default
; is kill. It can have a value of off or kill. In case of kill, all the existing
; threads are terminated and no new attempts are started. In case of off, the
; existing attempts keep on evaluating but no new attempts are started. This
; variable applies to only assert directives.
;AssertionThreadLimitAction = kill
; Cover thread limit after which cover would be killed/switched off.
; The default is -1 (unlimited). If the number of threads for a cover go
; beyond this limit, the cover would be either switched off or killed. This
; limit applies to only cover directives.
;CoverThreadLimit = -1
; Action to be taken once the cover thread limit is reached. Default
; is kill. It can have a value of off or kill. In case of kill, all the existing
; threads are terminated and no new attempts are started. In case of off, the
; existing attempts keep on evaluating but no new attempts are started. This
; variable applies to only cover directives.
;CoverThreadLimitAction = kill
; By default immediate assertions do not participate in Assertion Coverage calculations
; unless they are executed. This switch causes all immediate assertions in the design
; to participate in Assertion Coverage calculations, whether attempted or not.
; UnattemptedImmediateAssertions = 0
; By default immediate covers participate in Coverage calculations
; whether they are attempted or not. This switch causes all unattempted
; immediate covers in the design to stop participating in Coverage
; calculations.
; UnattemptedImmediateCovers = 0
; By default pass action block is not executed for assertions on vacuous
; success. The following variable is provided to enable execution of
; pass action block on vacuous success. The following variable is only effective
; if the user does not disable pass action block execution by using either
; system tasks or CLI. Also there is a performance penalty for enabling
; the following variable.
;AssertionEnableVacuousPassActionBlock = 1
; As per strict 1850-2005 PSL LRM, an always property can either pass
; or fail. However, by default, Questa reports multiple passes and
; multiple fails on top always/never property (always/never operator
; is the top operator under Verification Directive). The reason
; being that Questa reports passes and fails on per attempt of the
; top always/never property. Use the following flag to instruct
; Questa to strictly follow LRM. With this flag, all assert/never
; directives will start an attempt once at start of simulation.
; The attempt can either fail, match or match vacuously.
; For e.g. if always is the top operator under assert, the always will
; keep on checking the property at every clock. If the property under
; always fails, the directive will be considered failed and no more
; checking will be done for that directive. A top always property,
; if it does not fail, will show a pass at end of simulation.
; The default value is '0' (i.e. zero is off). For example:
; PslOneAttempt = 1
; Specify the number of clock ticks to represent infinite clock ticks.
; This affects eventually!, until! and until_!. If at End of Simulation
; (EOS) an active strong-property has not clocked this number of
; clock ticks then neither pass or fail (vacuous match) is returned
; else respective fail/pass is returned. The default value is '0' (zero)
; which effectively does not check for clock tick condition. For example:
; PslInfinityThreshold = 5000
; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance. Default is -1 (ALL).
; ATVStartTimeKeepCount = -1
; Turn on/off code coverage
; CodeCoverage = 0
; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1
; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100
; Set the maximum number of values that are collected for toggle coverage of
; Verilog real. Default is 100;
; ToggleMaxRealValues = 100
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to include them.
; ToggleVlogIntegers = 0
; Turn on automatic inclusion of Verilog real type in toggle coverage, except
; for shortreal types. Default is to not include them.
; ToggleVlogReal = 1
; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
; and VHDL arrays-of-arrays in toggle coverage.
; Default is to not include them.
; ToggleFixedSizeArray = 1
; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
; Default is 1024.
; ToggleMaxFixedSizeArray = 1024
; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
; one-dimensional packed vectors for toggle coverage. Default is 0.
; TogglePackedAsVec = 0
; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
; toggle coverage. Default is 0.
; ToggleVlogEnumBits = 0
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1
; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
; Following is the toggle coverage calculation criteria based on extended toggle mode:
; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
; ExtendedToggleMode = 3
; Enable toggle statistics collection only for ports. Default is 0.
; TogglePortsOnly = 1
; Turn on/off all PSL/SVA cover directive enables. Default is on.
; CoverEnable = 0
; Turn on/off PSL/SVA cover log. Default is off "0".
; CoverLog = 1
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
; CoverAtLeast = 2
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1
; Specify the coverage database filename.
; Default is "" (i.e. database is NOT automatically saved on close).
; UCDBFilename = vsim.ucdb
; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
; setting.
; MaxReportRhsSVCrossProducts = 1000
; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64
; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0
; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then
; cross_num_print_missing is ignored for creating reports and displaying
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0
; Specify the threshold of Coverpoint wildcard bin value range size, above which
; a warning will be triggered. The default is 4K -- 12 wildcard bits.
; SVCoverpointWildCardBinValueSizeWarn = 4096
; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0
; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100
; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100
; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
; builtin functions, and report. This setting changes the default values of
; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
; behavior if explicit assignments are not made on option.get_inst_coverage and
; type_option.merge_instances by the user. There are two vsim command line
; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
; The default value of this variable from release 6.6 onwards is 0. This default
; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
; SVCovergroup63Compatibility = 0
; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
; functions, GUI, and report. This setting changes the default values of
; type_option.merge_instances to ensure the 6.5 default behavior if explicit
; assignments are not made on type_option.merge_instances by the user.
; There are two vsim command line options, -cvgmergeinstances and
; -nocvgmergeinstances to override this setting from vsim command line.
; The default value of this variable from release 6.6 onwards is 0. This default
; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
; SvCovergroupMergeInstancesDefault = 1
; Enable or disable generation of more detailed information about the sampling
; of covergroup, cross, and coverpoints. It provides the details of the number
; of times the covergroup instance and type were sampled, as well as details
; about why covergroup, cross and coverpoint were not covered. A non-zero value
; is to enable this feature. 0 is to disable this feature. Default is 0
; SVCovergroupSampleInfo = 0
; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
; MaxSVCoverpointBinsInst = 2147483648
; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648
; Specify maximum number of Cross bins in any instance of a Covergroup
; MaxSVCrossBinsInst = 2147483648
; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
; By default, this variable is set 0, in which case option.no_collect setting will take effect.
; If this variable is set to 1, all zero-weight coverage items will not be saved.
; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
; of this variable.
; CvgZWNoCollect = 1
; Specify a space delimited list of double quoted TCL style
; regular expressions which will be matched against the text of all messages.
; If any regular expression is found to be contained within any message, the
; status for that message will not be propagated to the UCDB TESTSTATUS.
; If no match is detected, then the status will be propagated to the
; UCDB TESTSTATUS. More than one such regular expression text is allowed,
; and each message text is compared for each regular expression in the list.
; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
; Set weight for all PSL/SVA cover directives. Default is 1.
; CoverWeight = 2
; Check vsim plusargs. Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
; Run the 0in tools from within the simulator.
; Default is off.
; ZeroIn = 1
; Set the options to be passed to the 0in runtime tool.
; Default value set to "".
; ZeroInOptions = ""
; Initial seed for the random number generator of the root thread (SystemVerilog).
; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
; The default value is 0.
; Sv_Seed = 0
; Specify the solver "engine" that vsim will select for constrained random
; generation.
; Valid values are:
; "auto" - automatically select the best engine for the current
; constraint scenario
; "bdd" - evaluate all constraint scenarios using the BDD solver engine
; "act" - evaluate all constraint scenarios using the ACT solver engine
; While the BDD solver engine is generally efficient with constraint scenarios
; involving bitwise logical relationships, the ACT solver engine can exhibit
; superior performance with constraint scenarios involving large numbers of
; random variables related via arithmetic operators (+, *, etc).
; NOTE: This variable can be overridden with the vsim "-solveengine" command
; line switch.
; The default value is "auto".
; SolveEngine = auto
; Specify if the solver should attempt to ignore overflow/underflow semantics
; for arithmetic constraints (multiply, addition, subtraction) in order to
; improve performance. The "solveignoreoverflow" attribute can be specified on
; a per-call basis to randomize() to override this setting.
; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
; ignore overflow/underflow.
; SolveIgnoreOverflow = 0
; Specifies the maximum size that a dynamic array may be resized to by the
; solver. If the solver attempts to resize a dynamic array to a size greater
; than the specified limit, the solver will abort with an error.
; The default value is 2000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 2000
; Error message severity when randomize() failure is detected (SystemVerilog).
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; The default is 0 (no error).
; SolveFailSeverity = 0
; Enable/disable debug information for randomize() failures.
; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
; line switch.
; The default is 0 (disabled). Set to 1 to enable.
; SolveFailDebug = 0
; Specify the maximum size of the solution graph generated by the BDD solver.
; This value can be used to force the BDD solver to abort the evaluation of a
; complex constraint scenario that cannot be evaluated with finite memory.
; This value is specified in 1000s of nodes.
; The default value is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000
; Specify the maximum number of evaluations that may be performed on the
; solution graph by the BDD solver. This value can be used to force the BDD
; solver to abort the evaluation of a complex constraint scenario that cannot
; be evaluated in finite time. This value is specified in 10000s of evaluations.
; The default value is 10000. A value of 0 indicates no limit.
; SolveGraphMaxEval = 10000
; Specify the maximum number of tests that the ACT solver may evaluate before
; abandoning an attempt to solve a particular constraint scenario.
; The default value is 2000000. A value of 0 indicates no limit.
; SolveACTMaxTests = 2000000
; Specify the maximum number of operations that the ACT solver may perform
; before abandoning an attempt to solve a particular constraint scenario. The
; value is specified in 1000000s of operations.
; The default value is 10000. A value of 0 indicates no limit.
; SolveACTMaxOps = 10000
; Specify the number of times the ACT solver will retry to evaluate a constraint
; scenario that fails due to the SolveACTMaxTests threshold.
; The default value is 0 (no retry).
; SolveACTRetryCount = 0
; SolveSpeculateLevel controls whether or not the solver performs speculation
; during the evaluation of a constraint scenario.
; Speculation is an attempt to partition complex constraint scenarios by
; choosing a 'speculation' subset of the variables and constraints. This
; 'speculation' set is solved independently of the remaining constraints.
; The solver then attempts to solve the remaining variables and constraints
; (the 'dependent' set). If this attempt fails, the solver backs up and
; re-solves the 'speculation' set, then retries the 'dependent' set.
; Valid values are:
; 0 - no speculation
; 1 - enable speculation that maintains LRM specified distribution
; 2 - enable other speculation - may yield non-LRM distribution
; Currently, distribution constraints and solve-before constraints are
; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
; compliant speculation includes random variables in condition expressions.
; The default value is 0.
; SolveSpeculateLevel = 0
; By default, when speculation is enabled, the solver first tries to solve a
; constraint scenario *without* speculation. If the solver fails to evaluate
; the constraint scenario (due to time/memory limits) then the solver will
; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
; is set to 1, the solver will skip the initial non-speculative attempt to
; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
; non-zero)
; The default value is 0.
; SolveSpeculateFirst = 0
; Specify the maximum bit width of a variable in a conditional expression that
; may be considered as the basis for "conditional" speculation. (Only applies
; when SolveSpeculateLevel=2)
; The default value is 6.
; SolveSpeculateMaxCondWidth = 6
; Specify the maximum number of attempts to solve a speculative set of random
; variables and constraints. Exceeding this limit will cause the solver to
; abandon the current speculative set. (Only applies when SolveSpeculateLevel
; is non-zero)
; The default value is 100.
; SolveSpeculateMaxIterations = 100
; Specifies whether to attempt speculation on solve-before constraints or
; distribution constraints first. A value of 0 specifies that solve-before
; constraints are attempted first as the basis for speculative randomization.
; A value of 1 specifies that distribution constraints are attempted first
; as the basis for speculative randomization.
; The default value is 0.
; SolveSpeculateDistFirst = 0
; If the non-speculative BDD solver fails to evaluate a constraint scenario
; (due to time/memory limits) then the solver can be instructed to automatically
; re-evaluate the constraint scenario with the ACT solver engine. Set
; SolveACTbeforeSpeculate to 1 to enable this feature.
; The default value is 0 (do not re-evaluate with the ACT solver).
; SolveACTbeforeSpeculate = 0
; Use SolveFlags to specify options that will guide the behavior of the
; constraint solver. These options may improve the performance of the
; constraint solver for some testcases, and decrease the performance of the
; constraint solver for others.
; Valid flags are:
; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
; n = disable bit interleaving for all constraints (BDD engine)
; r = reverse bit interleaving (BDD engine)
; The default value is "" (no options).
; SolveFlags =
; Specify random sequence compatiblity with a prior letter release. This
; option is used to get the same random sequences during simulation as
; as a prior letter release. Only prior letter releases (of the current
; number release) are allowed.
; NOTE: Only those random sequence changes due to solver optimizations are
; reverted by this variable. Random sequence changes due to solver bugfixes
; cannot be un-done.
; NOTE: This variable can be overridden with the vsim "-solverev" command
; line switch.
; Default value set to "" (no compatibility).
; SolveRev =
; Environment variable expansion of command line arguments has been depricated
; in favor shell level expansion. Universal environment variable expansion
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this
; deprecated behavior. The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0
; Turn on/off collapsing of bus ports in VCD dumpports output
DumpportsCollapse = 1
; Location of Multi-Level Verification Component (MVC) installation.
; The default location is the product installation directory.
MvcHome = $MODEL_TECH/..
; Initialize SystemVerilog enums using the base type's default value
; instead of the leftmost value.
; EnumBaseInit = 1
; Suppress file type registration.
; SuppressFileTypeReg = 1
; Controls SystemVerilog Language Extensions. These options enable
; some non-LRM compliant behavior. Valid extensions are "feci",
; "pae", "uslt" and "spsl".
; SVExtensions = uslt,spsl
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; suppress can be used to achieve +nowarn<CODE> functionality
; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
; Examples:
suppress = 8780 ;an explanation can be had by running: verror 8780
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; suppress = 3009,CNNODP,3043,TFMPC
; suppress = 8683,8684
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of Verilog display system task messages and
; PLI/FLI print function call messages. The system tasks include
; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
; also include the analogous file I/O tasks that write to STDOUT
; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
; is to have messages appear only in the transcript. The other
; settings are to send messages to the wlf file only (messages that
; are recorded in the wlf file can be viewed in the MsgViewer) or
; to both the transcript and the wlf file. The valid values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; displaymsgmode = tran
; Control transcripting of elaboration/runtime messages not
; addressed by the displaymsgmode setting. The default is to
; have messages appear only in the transcript. The other settings
; are to send messages to the wlf file only (messages that are
; recorded in the wlf file can be viewed in the MsgViewer) or to both
; the transcript and the wlf file. The valid values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; msgmode = tran
syn/Release/temp_rise_counter.txt deleted 100644 → 0
View file @ b4f182b5
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/Release/testbench.udo deleted 100644 → 0
View file @ b4f182b5
######################################################################
##
## Filename: testbench.udo
## Created on: Tue Sep 06 16:30:52 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
syn/Release/testbench_envsettings.html deleted 100644 → 0
View file @ b4f182b5
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\EDA\Cadence\SPB_166\tools\pspice;<br>C:\EDA\Cadence\SPB_166\tools\capture;<br>C:\EDA\Cadence\SPB_166\tools\bin;<br>C:\EDA\Cadence\SPB_166\openaccess\bin\win32\opt;<br>C:\EDA\Cadence\SPB_166\tools\fet\bin;<br>C:\EDA\Cadence\SPB_166\tools\pcb\bin;<br>C:\EDA\Cadence\SPB_166\tools\specctra\bin;<br>C:\EDA\Cadence\SPB_166\tools\libutil\bin;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Users\debouhir\Documents\MikTex\miktex\bin\;<br>C:\Program Files\wbgen2-bin.tar\bin;<br>C:\Program Files\Git\cmd;<br>C:\VXIPNP\WinNT\Bin;<br>C:\modeltech64_10.1c\win64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>2112@lxlicen01,2112@lxlicen02,2112@lxlicen03</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>conv_ttl_blo.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>conv_ttl_blo</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx45t-3-fgg484</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>conv_ttl_blo</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-power</td>
<td>Power Reduction</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-dsp_utilization_ratio</td>
<td>DSP Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-reduce_control_sets</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_dsp48</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>100000</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>16</td>
<td>16</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Xeon(R) CPU E5620 @ 2.40GHz/2394 MHz</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>Host</td>
<td>PCBE15575</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 1 (build 7601)</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
syn/Release/testbench_summary.html deleted 100644 → 0
View file @ b4f182b5
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>conv_ttl_blo Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New (Failed)</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\testbench_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 7. Feb 16:41:32 2017</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/13/2017 - 18:37:49</center>
</BODY></HTML>
\ No newline at end of file
syn/Release/testbench_wave.fdo deleted 100644 → 0
View file @ b4f182b5
######################################################################
##
## Filename: testbench_wave.fdo
## Created on: Tue Sep 06 17:26:22 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
#add wave /glbl/GSR
syn/Release/transcript deleted 100644 → 0
View file @ b4f182b5
This source diff could not be displayed because it is too large. You can view the blob instead.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment