hdl: Made manual pulse triggering safer

This was done by reading the whole value of the 8-bit MPT field after the magic sequence is input. Before, only the number of bits corresponding to the number of channels at the input was read, which could result in a pulse being generated when a wrong channel value with a "correct" mask is input to the field, as for example: - on the six-channel CONV-TTL-BLO, 0x9 in MPT gets masked on three bits to 0x1, thus a pulse is generated on CH1 Signed-off-by: Theodor Stana <t.stana@cern.ch>

hdl: Made manual pulse triggering safer
This was done by reading the whole value of the 8-bit MPT field after the magic sequence is input. Before, only the number of bits corresponding to the number of channels at the input was read, which could result in a pulse being generated when a wrong channel value with a "correct" mask is input to the field, as for example: - on the six-channel CONV-TTL-BLO, 0x9 in MPT gets masked on three bits to 0x1, thus a pulse is generated on CH1 Signed-off-by: Theodor Stana <t.stana@cern.ch>
a9306cba · Theodor-Adrian Stana · b488cf13 · a9306cba
Commit a9306cba authored Feb 03, 2014 by Theodor-Adrian Stana
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conv_man_trig.vhd modules/Release/conv_man_trig.vhd +6 -13

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--- a/modules/Release/conv_man_trig.vhd
+++ b/modules/Release/conv_man_trig.vhd
@@ -143,9 +143,7 @@ architecture behav of conv_man_trig is
  -- Signal for the current state of the FSM
  signal state : t_state;

-  -- "Password" and channel number signals
-  signal pass  : std_logic_vector(7 downto 0);
-  signal chnr  : std_logic_vector(f_log2_size(g_nr_chan)-1 downto 0);
+  -- Counter to extend the pulse to the needed number of channels
  signal cnt   : unsigned(f_log2_size(g_gf_len)-1 downto 0);

 --==============================================================================
@@ -156,11 +154,6 @@ begin
  --============================================================================
  -- FSM logic
  --============================================================================
-  -- First, assign the password, channel enable and channel number signals
-  pass <= reg_i;
-  chnr <= reg_i(f_log2_size(g_nr_chan)-1 downto 0);
-
-  -- Then, the process for the FSM
  p_fsm : process (clk_i)
  begin
    if rising_edge(clk_i) then
@@ -172,17 +165,17 @@ begin
        case state is
          when IDLE =>
            trig_o <= (others => '0');
-            f_change_state(reg_ld_i, pass, 0, state, PASS1);
+            f_change_state(reg_ld_i, reg_i, 0, state, PASS1);
          when PASS1 =>
-            f_change_state(reg_ld_i, pass, 1, state, PASS2);
+            f_change_state(reg_ld_i, reg_i, 1, state, PASS2);
          when PASS2 =>
-            f_change_state(reg_ld_i, pass, 2, state, PASS3);
+            f_change_state(reg_ld_i, reg_i, 2, state, PASS3);
          when PASS3 =>
-            f_change_state(reg_ld_i, pass, 3, state, GET_CHAN);
+            f_change_state(reg_ld_i, reg_i, 3, state, GET_CHAN);
          when GET_CHAN =>
            if (reg_ld_i = '1') then
              for i in 1 to g_nr_chan loop
-                if i = to_integer(unsigned(chnr)) then
+                if (i = to_integer(unsigned(reg_i))) then
                  trig_o(i) <= '1';
                end if;
              end loop;