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Conv TTL Blocking - Gateware
Commit a49147ad authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Added project file and manifest in ./syn folder

parent dba7f4b0
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syn/Release/Makefile 0 → 100644
View file @ a49147ad
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo.xise
ISE_CRAP := *.b conv_ttl_blo_summary.html *.tcl conv_ttl_blo.bld conv_ttl_blo.cmd_log *.drc conv_ttl_blo.lso *.ncd conv_ttl_blo.ngc conv_ttl_blo.ngd conv_ttl_blo.ngr conv_ttl_blo.pad conv_ttl_blo.par conv_ttl_blo.pcf conv_ttl_blo.prj conv_ttl_blo.ptwx conv_ttl_blo.stx conv_ttl_blo.syr conv_ttl_blo.twr conv_ttl_blo.twx conv_ttl_blo.gise conv_ttl_blo.unroutes conv_ttl_blo.ut conv_ttl_blo.xpi conv_ttl_blo.xst conv_ttl_blo_bitgen.xwbt conv_ttl_blo_envsettings.html conv_ttl_blo_guide.ncd conv_ttl_blo_map.map conv_ttl_blo_map.mrp conv_ttl_blo_map.ncd conv_ttl_blo_map.ngm conv_ttl_blo_map.xrpt conv_ttl_blo_ngdbuild.xrpt conv_ttl_blo_pad.csv conv_ttl_blo_pad.txt conv_ttl_blo_par.xrpt conv_ttl_blo_summary.xml conv_ttl_blo_usage.xml conv_ttl_blo_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
syn/Release/Manifest.py 0 → 100644
View file @ a49147ad
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../../top/Release"
]
}
syn/Release/conv_ttl_blo.xise 0 → 100644
View file @ a49147ad
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
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<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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<bindings/>
<libraries/>
<autoManagedFiles>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
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