Commit 9e8e0f9c authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Small mods to the top file, mainly cleanup and added pcb revision number

parent eb11aa6d
This diff is collapsed.
......@@ -84,7 +84,7 @@ entity conv_ttl_blo is
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(3 downto 0);
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
......@@ -335,17 +335,19 @@ begin
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
--Note that this burst mode functionality is activated only for PCB ver 4 or later
--Note that this burst mode functionality is activated only for PCB v4 or later
--The FPGA
-- Functionality enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
burst_en_n <= '0' when pcbrev_i >= "0100" --Functionality enabled for versions 4 and above
else '1'; --when version is below 4 then disable burst functionality
--This change needs to be deleted for gw release, only used oas a hack for v3 boards
-- burst_en_n <= '0' when sw_gp(6 downto 3)>="0100" --Functionality enabled for versions 4 and above
-- else '1'; --when version is below 4 then disable burst functionality
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
-- support v4 functionality
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--**************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
......@@ -362,15 +364,18 @@ begin
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_duty_cycle_div_cont=> 200,
g_pgen_duty_cycle_div_lg => 8, -- Minimum duty cycle supoported for 1.2us pulse ~ max freq 104kHz
g_pgen_duty_cycle_div_sh => 2, -- Minimum duty cycle supoported for 250ns pulse ~ max freq 2MHz
-- Minimum duty cycle supported for 1.2us pulse ~ max freq 104kHz
g_pgen_duty_cycle_div_lg => 8,
-- Minimum duty cycle supoported for 250ns pulse ~ max freq 2MHz
g_pgen_duty_cycle_div_sh => 2,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13),
g_temp_decre_step_sh => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"23040",
g_burstctrl_1_pulse_temp_rise_sh => x"01388",
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step_sh => (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"17700", --96000
g_burstctrl_1_pulse_temp_rise_sh => x"01388", --5000
g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
--g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
......@@ -462,9 +467,10 @@ begin
-- Switch inputs (for readout from converter status register)
sw_gp_i => sw_gp,
sw_other_i => (others => '0'),
-- PCB Version information
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment