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Conv TTL Blocking - Gateware
Commit 9e8e0f9c authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Small mods to the top file, mainly cleanup and added pcb revision number

parent eb11aa6d
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syn/Release/conv_ttl_blo.xise
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......@@ -20,7 +20,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
......@@ -36,7 +36,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
......@@ -56,15 +56,15 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
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......@@ -80,7 +80,7 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
......@@ -100,7 +100,7 @@
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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......@@ -108,11 +108,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
......@@ -124,7 +124,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
......@@ -136,7 +136,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
......@@ -144,15 +144,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
......@@ -180,11 +180,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
......@@ -192,7 +192,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
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......@@ -216,15 +216,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
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......@@ -444,23 +444,23 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
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......@@ -484,66 +484,62 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
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<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
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<file xil_pn:name="../../sim/Release/burst_ctrl_tb.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="131"/>
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<file xil_pn:name="../../sim/Release/i2c_bus_model.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="130"/>
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<file xil_pn:name="../../sim/Release/testbenchv4.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../top/Release/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../top/Release/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
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......@@ -739,7 +735,7 @@
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="-coverage" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -822,7 +818,7 @@
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1100ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="10ms" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
......@@ -900,15 +896,13 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-12-16T13:25:27" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0D1D5AB8A7664009B319D970D9BBE2BC" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-02-07T16:30:27" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="64223241A98F4D938606EC70F10B22B0" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/conv_ttl_blo" xil_pn:name="../../top/Release/conv_ttl_blo.ucf"/>
</bindings>
<bindings/>
<libraries/>
......
top/Release/conv_ttl_blo.vhd
View file @ 9e8e0f9c
......@@ -84,7 +84,7 @@ entity conv_ttl_blo is
vme_gap_i : in std_logic;
-- PCB version recognition
pcbrev_i : in std_logic_vector(3 downto 0);
pcbrev_i : in std_logic_vector(5 downto 0);
-- Channel enable
global_oen_o : out std_logic;
......@@ -335,17 +335,19 @@ begin
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
--Note that this burst mode functionality is activated only for PCB ver 4 or later
--Note that this burst mode functionality is activated only for PCB v4 or later
--The FPGA
burst_en_n <= '0' when pcbrev_i >= "0100" --Functionality enabled for versions 4 and above
else '1'; --when version is below 4 then disable burst functionality
--This change needs to be deleted for gw release, only used oas a hack for v3 boards
-- burst_en_n <= '0' when sw_gp(6 downto 3)>="0100" --Functionality enabled for versions 4 and above
-- else '1'; --when version is below 4 then disable burst functionality
-- Functionality enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
-- support v4 functionality
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--**************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
......@@ -362,15 +364,18 @@ begin
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_duty_cycle_div_cont=> 200,
g_pgen_duty_cycle_div_lg => 8, -- Minimum duty cycle supoported for 1.2us pulse ~ max freq 104kHz
g_pgen_duty_cycle_div_sh => 2, -- Minimum duty cycle supoported for 250ns pulse ~ max freq 2MHz
-- Minimum duty cycle supported for 1.2us pulse ~ max freq 104kHz
g_pgen_duty_cycle_div_lg => 8,
-- Minimum duty cycle supoported for 250ns pulse ~ max freq 2MHz
g_pgen_duty_cycle_div_sh => 2,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13),
g_temp_decre_step_sh => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"23040",
g_burstctrl_1_pulse_temp_rise_sh => x"01388",
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
g_temp_decre_step_sh => (0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"17700", --96000
g_burstctrl_1_pulse_temp_rise_sh => x"01388", --5000
g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
--g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
......@@ -462,9 +467,10 @@ begin
-- Switch inputs (for readout from converter status register)
sw_gp_i => sw_gp,
sw_other_i => (others => '0'),
-- PCB Version information
hwvers_i => pcbrev_i,
-- RTM lines
rtmm_i => rtmm_i,
rtmp_i => rtmp_i,
......
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