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Conv TTL Blocking - Gateware
Commit 9d2ca9ea authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Created golden branch to store golden firmware project files 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 68e5ac71
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modules/pulsetest/Manifest.py deleted 100644 → 0
View file @ 68e5ac71
files = [
"conv_regs.vhd",
"pulse_cnt_regs.vhd",
"pgen_ctrl_regs.vhd",
"pulse_gen_gp.vhd"
]
modules/pulsetest/conv_regs.vhd deleted 100644 → 0
View file @ 68e5ac71
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Sat Dec 7 14:11:02 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
reg_id_bits_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
reg_sr_fwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'Control Register'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_id_bits_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_sr_fwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
reg_cr_rst_unlock_load_o <= '1';
reg_cr_rst_load_o <= '1';
end if;
rddata_reg(0) <= reg_cr_rst_unlock_i;
rddata_reg(1) <= reg_cr_rst_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
-- fwvers
-- switches
-- RTM detection
-- I2C Watchdog Timeout
reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
reg_cr_rst_o <= wrdata_reg(1);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/pulsetest/conv_regs.wb deleted 100644 → 0
View file @ 68e5ac71
peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "reg";
reg {
name = "Board ID Register";
description = "Bits of ID register, defaulting to ASCII string TBLO";
prefix = "id";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Status Register";
description = "Contains various board status information";
prefix = "sr";
field {
name = "fwvers";
prefix = "fwvers";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "switches";
prefix = "switches";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "RTM detection";
prefix = "rtm";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "I2C Watchdog Timeout";
prefix = "i2c_wdto";
type = BIT;
size = 1;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Control Register";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
-- field {
-- name = "blocking chan 1 enable";
-- prefix = "bch1_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 2 enable";
-- prefix = "bch2_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 3 enable";
-- prefix = "bch3_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 4 enable";
-- prefix = "bch4_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 5 enable";
-- prefix = "bch5_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 6 enable";
-- prefix = "bch6_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
description = "1 - Reset bit unlocked\
0 - Reset bit locked";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Reset bit";
prefix = "rst";
description = "1 - initiate logic reset\
0 - no reset";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
modules/pulsetest/pgen_ctrl_regs.vhd deleted 100644 → 0
View file @ 68e5ac71
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse generation control registers
---------------------------------------------------------------------------------------
-- File : pgen_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from pgen_ctrl_regs.wb
-- Created : Fri Aug 16 11:22:20 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pgen_ctrl_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end pgen_ctrl_regs;
architecture syn of pgen_ctrl_regs is
signal pgen_ctrl_regs_en_ch_int : std_logic_vector(5 downto 0);
signal pgen_ctrl_regs_ch1_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_freq_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pgen_ctrl_regs_en_ch_int <= "000000";
pgen_ctrl_regs_ch1_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_freq_bits_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_en_ch_int <= wrdata_reg(5 downto 0);
end if;
rddata_reg(5 downto 0) <= pgen_ctrl_regs_en_ch_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- channel enable
pgen_ctrl_regs_en_ch_o <= pgen_ctrl_regs_en_ch_int;
-- bits
pgen_ctrl_regs_ch1_delay_bits_o <= pgen_ctrl_regs_ch1_delay_bits_int;
-- bits
pgen_ctrl_regs_ch2_delay_bits_o <= pgen_ctrl_regs_ch2_delay_bits_int;
-- bits
pgen_ctrl_regs_ch3_delay_bits_o <= pgen_ctrl_regs_ch3_delay_bits_int;
-- bits
pgen_ctrl_regs_ch4_delay_bits_o <= pgen_ctrl_regs_ch4_delay_bits_int;
-- bits
pgen_ctrl_regs_ch5_delay_bits_o <= pgen_ctrl_regs_ch5_delay_bits_int;
-- bits
pgen_ctrl_regs_ch6_delay_bits_o <= pgen_ctrl_regs_ch6_delay_bits_int;
-- bits
pgen_ctrl_regs_ch1_pwidth_bits_o <= pgen_ctrl_regs_ch1_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch2_pwidth_bits_o <= pgen_ctrl_regs_ch2_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch3_pwidth_bits_o <= pgen_ctrl_regs_ch3_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch4_pwidth_bits_o <= pgen_ctrl_regs_ch4_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch5_pwidth_bits_o <= pgen_ctrl_regs_ch5_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch6_pwidth_bits_o <= pgen_ctrl_regs_ch6_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch1_freq_bits_o <= pgen_ctrl_regs_ch1_freq_bits_int;
-- bits
pgen_ctrl_regs_ch2_freq_bits_o <= pgen_ctrl_regs_ch2_freq_bits_int;
-- bits
pgen_ctrl_regs_ch3_freq_bits_o <= pgen_ctrl_regs_ch3_freq_bits_int;
-- bits
pgen_ctrl_regs_ch4_freq_bits_o <= pgen_ctrl_regs_ch4_freq_bits_int;
-- bits
pgen_ctrl_regs_ch5_freq_bits_o <= pgen_ctrl_regs_ch5_freq_bits_int;
-- bits
pgen_ctrl_regs_ch6_freq_bits_o <= pgen_ctrl_regs_ch6_freq_bits_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/pulsetest/pgen_ctrl_regs.wb deleted 100644 → 0
View file @ 68e5ac71
peripheral {
name = "Pulse generation control registers";
description = "Registers containing control signals for the general-purpose pulse generator blocks";
hdl_entity = "pgen_ctrl_regs";
prefix = "pgen_ctrl_regs";
reg {
name = "Enable register";
prefix = "en";
field {
name = "channel enable";
prefix = "ch";
type = SLV;
size = 6;
};
};
reg {
name = "CH1 delay register";
prefix = "ch1_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 delay register";
prefix = "ch2_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 delay register";
prefix = "ch3_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 delay register";
prefix = "ch4_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 delay register";
prefix = "ch5_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 delay register";
prefix = "ch6_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 pulse width register";
prefix = "ch1_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 pulse width register";
prefix = "ch2_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 pulse width register";
prefix = "ch3_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 pulse width register";
prefix = "ch4_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 pulse width register";
prefix = "ch5_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 pulse width register";
prefix = "ch6_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 frequency register";
prefix = "ch1_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 frequency register";
prefix = "ch2_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 frequency register";
prefix = "ch3_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 frequency register";
prefix = "ch4_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 frequency register";
prefix = "ch5_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 frequency register";
prefix = "ch6_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
};
modules/pulsetest/pulse_cnt_regs.vhd deleted 100644 → 0
View file @ 68e5ac71
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse counter registers
---------------------------------------------------------------------------------------
-- File : pulse_cnt_regs.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_regs.wb
-- Created : Mon Sep 16 18:23:47 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o : out std_logic
);
end pulse_cnt_regs;
architecture syn of pulse_cnt_regs is
signal pulse_cnt_rst_bit_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pulse_cnt_rst_bit_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
pulse_cnt_rst_bit_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= pulse_cnt_rst_bit_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- reset
pulse_cnt_rst_bit_o <= pulse_cnt_rst_bit_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/pulsetest/pulse_cnt_regs.wb deleted 100644 → 0
View file @ 68e5ac71
peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_regs";
prefix = "pulse_cnt";
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Counter reset";
prefix = "rst";
field {
name = "reset";
prefix = "bit";
type = BIT;
};
};
};
modules/pulsetest/pulse_gen_gp.vhd deleted 100644 → 0
View file @ 68e5ac71
--==============================================================================
-- CERN (BE-CO-HT)
-- General-purpose pulse generator
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 2.0
--
-- description:
--
-- This module generates pulses with configurable frequency, width and delay.
--
-- In order to generate pulses, the module must be enabled via the en_i port.
-- Once en_i is high, pulses are generated at the frequency specified via
-- freq_i, with the width specified via pwidth_i.
--
-- An optional delay can be added before the start of the pulse, via the delay_i
-- port.
--
-- Note that this delay can be set only before the module is enabled.
--
-- freq_i, pwidth_i and delay_i are given in clk_i cycles.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
-- 2013 08-15 Theodor Stana t.stana@cern.ch v2.0, delay, pwidth, freq
-- now controllable via
-- inputs (regs, etc.)
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen_gp is
port
(
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end entity pulse_gen_gp;
architecture behav of pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal inp_delay : unsigned(31 downto 0);
signal inp_pwidth : unsigned(31 downto 0);
signal inp_freq : unsigned(31 downto 0);
signal freq_cnt : unsigned(31 downto 0);
signal delay_cnt : unsigned(31 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Convert std_logic_vector inputs to unsigned
--============================================================================
inp_delay <= unsigned(delay_i);
inp_pwidth <= unsigned(pwidth_i);
inp_freq <= unsigned(freq_i);
--============================================================================
-- Delay logic
--============================================================================
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
else
if (inp_delay = (inp_delay'range => '0')) then
delay_en <= '0';
elsif (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = inp_delay) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end if;
end process p_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
freq_cnt <= (others => '0');
pulse_o <= '0';
elsif (delay_en = '0') then
freq_cnt <= freq_cnt + 1;
pulse_o <= '0';
if (freq_cnt < inp_pwidth) then
pulse_o <= '1';
elsif (freq_cnt = inp_freq-1) then
freq_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
syn/Release/Makefile → syn/Golden/Makefile
View file @ 9d2ca9ea
......@@ -36,8 +36,8 @@ endif
CWD := $(shell pwd)
FILES := ../../top/Release/conv_ttl_blo.ucf \
../../top/Release/conv_ttl_blo.vhd \
FILES := ../../top/Golden/conv_ttl_blo.ucf \
../../top/Golden/conv_ttl_blo.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/ctb_pulse_gen.vhd \
../../modules/reset_gen.vhd \
......
syn/Release/Manifest.py → syn/Golden/Manifest.py
View file @ 9d2ca9ea
......@@ -8,6 +8,6 @@ syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../../top/Release"
"../../top/Golden"
]
}
syn/Release/conv_ttl_blo.xise → syn/Golden/conv_ttl_blo.xise
View file @ 9d2ca9ea
......@@ -175,7 +175,7 @@
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -202,7 +202,7 @@
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
......@@ -338,10 +338,10 @@
<libraries/>
<files>
<file xil_pn:name="../../top/Release/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../top/Golden/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../top/Release/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../top/Golden/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../modules/Release/conv_regs.vhd" xil_pn:type="FILE_VHDL">
......
syn/pulsetest/Makefile deleted 100644 → 0
View file @ 68e5ac71
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := pulsetest.xise
ISE_CRAP := *.b pulsetest_summary.html *.tcl pulsetest.bld pulsetest.cmd_log *.drc pulsetest.lso *.ncd pulsetest.ngc pulsetest.ngd pulsetest.ngr pulsetest.pad pulsetest.par pulsetest.pcf pulsetest.prj pulsetest.ptwx pulsetest.stx pulsetest.syr pulsetest.twr pulsetest.twx pulsetest.gise pulsetest.unroutes pulsetest.ut pulsetest.xpi pulsetest.xst pulsetest_bitgen.xwbt pulsetest_envsettings.html pulsetest_guide.ncd pulsetest_map.map pulsetest_map.mrp pulsetest_map.ncd pulsetest_map.ngm pulsetest_map.xrpt pulsetest_ngdbuild.xrpt pulsetest_pad.csv pulsetest_pad.txt pulsetest_par.xrpt pulsetest_summary.xml pulsetest_usage.xml pulsetest_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=pulsetest
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/pulsetest/pulsetest.ucf \
../../top/pulsetest/pulsetest.vhd \
../../modules/pulsetest/conv_regs.vhd \
../../modules/pulsetest/pulse_cnt_regs.vhd \
../../modules/pulsetest/pgen_ctrl_regs.vhd \
../../modules/pulsetest/pulse_gen_gp.vhd \
../../modules/ctb_pulse_gen.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
pulsetest.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/pulsetest/Manifest.py deleted 100644 → 0
View file @ 68e5ac71
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "pulsetest"
syn_project = "pulsetest.xise"
modules = {
"local" : [
"../../top/pulsetest"
]
}
syn/pulsetest/pulsetest.xise deleted 100644 → 0
View file @ 68e5ac71
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pulsetest" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
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<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
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<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
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<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
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<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="pulsetest" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
syn/regtest/Makefile deleted 100644 → 0
View file @ 68e5ac71
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := regtest.xise
ISE_CRAP := *.b regtest_summary.html *.tcl regtest.bld regtest.cmd_log *.drc regtest.lso *.ncd regtest.ngc regtest.ngd regtest.ngr regtest.pad regtest.par regtest.pcf regtest.prj regtest.ptwx regtest.stx regtest.syr regtest.twr regtest.twx regtest.gise regtest.unroutes regtest.ut regtest.xpi regtest.xst regtest_bitgen.xwbt regtest_envsettings.html regtest_guide.ncd regtest_map.map regtest_map.mrp regtest_map.ncd regtest_map.ngm regtest_map.xrpt regtest_ngdbuild.xrpt regtest_pad.csv regtest_pad.txt regtest_par.xrpt regtest_summary.xml regtest_usage.xml regtest_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=regtest
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/regtest/regtest.ucf \
../../top/regtest/regtest.vhd \
../../modules/ctb_pulse_gen.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
regtest.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/regtest/Manifest.py deleted 100644 → 0
View file @ 68e5ac71
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "regtest"
syn_project = "regtest.xise"
modules = {
"local" : [
"../../top/regtest"
]
}
syn/regtest/regtest.xise deleted 100644 → 0
View file @ 68e5ac71
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
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<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
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</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
top/Release/conv_ttl_blo.vhd → top/Golden/conv_ttl_blo.vhd
View file @ 9d2ca9ea
......@@ -7,7 +7,7 @@
-- author: Theodor Stana (t.stana@cern.ch)
-- Carlos-Gil-Soriano
--
-- version: 1.0
-- version: 0.0 -- golden firmware version
--
-- description:
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
......@@ -173,7 +173,8 @@ architecture behav of conv_ttl_blo is
-- next minor release v1.1 c_fwvers = x"11";
-- 13 minor releases later v1.14 c_fwvers = x"1e";
-- next major release v2.0 c_fwvers = x"20";
constant c_fwvers : std_logic_vector(7 downto 0) := x"10";
-- - version 0.0 is golden firmware version for MultiBoot fallback
constant c_fwvers : std_logic_vector(7 downto 0) := x"00";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
......
top/pulsetest/Manifest.py deleted 100644 → 0
View file @ 68e5ac71
files = [
"pulsetest.ucf",
"pulsetest.vhd"
]
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../modules/pulsetest",
"../../modules"
]
}
top/pulsetest/pulsetest.ucf deleted 100644 → 0
View file @ 68e5ac71
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
NET "fpga_clk_p_i" TNM_NET = "clk125";
TIMESPEC TSCLK125 = PERIOD "clk125" 125 MHz HIGH 50%;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- WHITE RABBIT
##=============================================================================
##-----------------------------------------------------------------------------
##-- Thermo for UID
##-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- DAC control
##-----------------------------------------------------------------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
# NET "fpga_rtmm_n_i[0]" LOC = V21;
# NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[1]" LOC = V22;
# NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[2]" LOC = U22;
# NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[0]" LOC = W22;
# NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[1]" LOC = Y22;
# NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[2]" LOC = Y21;
# NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
top/pulsetest/pulsetest.vhd deleted 100644 → 0
View file @ 68e5ac71
--==============================================================================
-- CERN (BE-CO-HT)
-- Long-term pulse test for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description:
-- This is the top-level file for the long-term pulse repetition test for TTL
-- pulse converter boards. All the top-level logic generation and component
-- instantiation is done here.
--
-- A general-purpose pulse generator component (pulse_gen_gp) is used to
-- generate the output pulses on the converter board output channels. One
-- such pulse generator is instantiated per channel and external logic is
-- used to adapt these pulses for TTL or TTL-BAR signals.
--
-- The characteristics of pulses generated by the generators can be
-- controlled by means of registers accessible over the I2C bus on the
-- VME backplanes. To access the registers, the protocol defined together
-- with ELMA [2] is used and the wb_i2c_bridge component handles translating
-- this protocol into the Wishbone protocol, which is then used to access
-- the registers controlling the pulse generators.
--
-- An example test script can be used to run the long-term pulse repetition
-- test. The test script can be found in the software/pulsetest/ folder in
-- the conv-ttl-blo repository [3]. More information on what the script does
-- can be found on the CONV-TTL-BLO Testing webpage [4].
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
-- [3] CONV-TTL-BLO project repository on OHWR,
-- http://www.ohwr.org/projects/conv-ttl-blo/repository
-- [4] CONV-TTL-BLO Test page on OHWR,
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/Testing
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity pulsetest is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end pulsetest;
architecture behav of pulsetest is
--============================================================================
-- Type declarations
--============================================================================
type t_pulse_counter is array(1 to g_nr_ttl_chan) of unsigned(31 downto 0);
type t_pulse_led_cnt is array (1 to g_nr_ttl_chan) of unsigned(18 downto 0);
type t_pgen_ctrl_reg is array (1 to 6) of std_logic_vector(31 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Board ID - ASCII string "TBLO"
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-- Firmware version
-- - format: M.m
-- - M: major version hex number (e.g. 1)
-- - m: minor version hex number (e.g. 13)
-- - example: first major release v1.0 c_fwvers = x"10";
-- next minor release v1.1 c_fwvers = x"11";
-- 13 minor releases later v1.12 c_fwvers = x"1e";
-- next major release v2.0 c_fwvers = x"20";
-- Test firmware gets numbered from v9.9 downward
-- The pulse test firmware is v9.9
constant c_fwvers : std_logic_vector(7 downto 0) := x"99";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 4;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- CONV_REGS [0x000-0x004]
-- PULSE_CNT [0x100-0x13F]
-- PGEN_CTRL [0x200-0x24F]
-- MULTIBOOT [0x300-0x31F]
-----------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_pulse_cnt : natural := 1;
constant c_slv_pgen_ctrl : natural := 2;
constant c_slv_multiboot : natural := 3;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_pulse_cnt : t_wishbone_address := x"00000100";
constant c_addr_pgen_ctrl : t_wishbone_address := x"00000200";
constant c_addr_multiboot : t_wishbone_address := x"00000300";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000F00";
constant c_mask_pulse_cnt : t_wishbone_address := x"00000F00";
constant c_mask_pgen_ctrl : t_wishbone_address := x"00000F00";
constant c_mask_multiboot : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_pulse_cnt => c_addr_pulse_cnt,
c_slv_pgen_ctrl => c_addr_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_pulse_cnt => c_mask_pulse_cnt,
c_slv_pgen_ctrl => c_mask_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- Converter registers
-- (use: ID, firmware version)
component conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID Register'
reg_id_bits_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status Register'
reg_sr_fwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status Register'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status Register'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C Watchdog Timeout' in reg: 'Status Register'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control Register'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'Control Register'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic
);
end component conv_regs;
-- General-purpose pulse generator component
-- (usage: generate pulses on each channel output)
component pulse_gen_gp is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
pulse_o : out std_logic
);
end component pulse_gen_gp;
-- Pulse generator control registers component
-- (usage: contains bits and values to control the pulse_gen_gp component)
component pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end component pgen_ctrl_regs;
-- Pulse counter registers component
-- (usage: store values of pulse counters)
component pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o : out std_logic
);
end component pulse_cnt_regs;
-- MultiBoot component
-- use: remotely reprogram the FPGA
component wb_xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component wb_xil_multiboot;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signals
signal rst_n : std_logic;
signal rst_unlock : std_logic;
signal rst_unlock_bit : std_logic;
signal rst_unlock_bit_ld : std_logic;
signal rst_bit : std_logic;
signal rst_bit_ld : std_logic;
signal rst_fr_reg : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches_n : std_logic_vector(7 downto 0);
signal wdto_bit : std_logic;
signal wdto_bit_rst : std_logic;
signal wdto_bit_rst_ld : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- VBCP bridge signals
signal i2c_tip : std_logic;
signal i2c_err_p : std_logic;
signal i2c_wdto_p : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(18 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal led_i2c_blink : std_logic;
signal led_i2c_err : std_logic;
-- Pulse enable signals
signal oe, ttl_oe : std_logic;
signal blo_oe, inv_oe : std_logic;
signal ch_en : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse generation signals
signal trig_ttl_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse, pulse_d0 : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_r_edge_p : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse LED signals
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_cnt : t_pulse_led_cnt;
-- Pulse generator and counter register signals
signal cnt_in, cnt_out : t_pulse_counter;
signal cntrst : std_logic;
signal delay_reg : t_pgen_ctrl_reg;
signal pwidth_reg : t_pgen_ctrl_reg;
signal freq_reg : t_pgen_ctrl_reg;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
)
port map
(
clk_i => clk20_vcxo_i,
rst_i => rst_fr_reg,
rst_n_o => rst_n
);
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : wb_i2c_bridge
port map
(
-- Clock, reset
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_oe_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_oe_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
led_i2c_blink <= '0';
else
case led_i2c_blink is
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
end if;
when others =>
led_i2c_blink <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_err <= '0';
elsif (i2c_err_p = '1') then
led_i2c_err <= '1';
end if;
end if;
end process p_i2c_err_led;
-- Register for the WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
wdto_bit <= '1';
elsif (wdto_bit_rst_ld = '1') and (wdto_bit_rst = '1') then
wdto_bit <= '0';
end if;
end if;
end process p_sr_wdto_bit;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk20_vcxo_i,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Converter board registers
--============================================================================
-- Set SWITCH and RTM fields
switches_n <= ttl_switch_n_i & extra_switch_n_i(7 downto 1);
rtm_lines <= rtmp & rtmm;
-- Then, instantiate the component
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_n,
clk_sys_i => clk20_vcxo_i,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(3 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
reg_id_bits_i => c_board_id,
reg_sr_fwvers_i => c_fwvers,
reg_sr_switches_i => switches_n,
reg_sr_rtm_i => rtm_lines,
reg_sr_i2c_wdto_o => wdto_bit_rst,
reg_sr_i2c_wdto_i => wdto_bit,
reg_sr_i2c_wdto_load_o => wdto_bit_rst_ld,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
reg_cr_rst_unlock_load_o => rst_unlock_bit_ld,
reg_cr_rst_o => rst_bit,
reg_cr_rst_i => rst_fr_reg,
reg_cr_rst_load_o => rst_bit_ld
);
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
rst_unlock <= '0';
elsif (rst_unlock_bit_ld = '1') then
if (rst_unlock_bit = '1') then
rst_unlock <= '1';
else
rst_unlock <= '0';
end if;
end if;
end if;
end process p_rst_unlock;
-- And implement the reset bit register
p_rst_fr_reg : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
rst_fr_reg <= '0';
elsif (rst_bit_ld = '1') and (rst_bit = '1') and (rst_unlock = '1') then
rst_fr_reg <= '1';
end if;
end if;
end process p_rst_fr_reg;
--============================================================================
-- Pulse generation control registers instantiation
--============================================================================
cmp_pulse_gen_ctrl_regs : pgen_ctrl_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk20_vcxo_i,
wb_adr_i => xbar_master_out(c_slv_pgen_ctrl).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_pgen_ctrl).dat,
wb_dat_o => xbar_master_in(c_slv_pgen_ctrl).dat,
wb_cyc_i => xbar_master_out(c_slv_pgen_ctrl).cyc,
wb_sel_i => xbar_master_out(c_slv_pgen_ctrl).sel,
wb_stb_i => xbar_master_out(c_slv_pgen_ctrl).stb,
wb_we_i => xbar_master_out(c_slv_pgen_ctrl).we,
wb_ack_o => xbar_master_in(c_slv_pgen_ctrl).ack,
wb_stall_o => xbar_master_in(c_slv_pgen_ctrl).stall,
pgen_ctrl_regs_en_ch_o => ch_en,
pgen_ctrl_regs_ch1_delay_bits_o => delay_reg(1),
pgen_ctrl_regs_ch2_delay_bits_o => delay_reg(2),
pgen_ctrl_regs_ch3_delay_bits_o => delay_reg(3),
pgen_ctrl_regs_ch4_delay_bits_o => delay_reg(4),
pgen_ctrl_regs_ch5_delay_bits_o => delay_reg(5),
pgen_ctrl_regs_ch6_delay_bits_o => delay_reg(6),
pgen_ctrl_regs_ch1_pwidth_bits_o => pwidth_reg(1),
pgen_ctrl_regs_ch2_pwidth_bits_o => pwidth_reg(2),
pgen_ctrl_regs_ch3_pwidth_bits_o => pwidth_reg(3),
pgen_ctrl_regs_ch4_pwidth_bits_o => pwidth_reg(4),
pgen_ctrl_regs_ch5_pwidth_bits_o => pwidth_reg(5),
pgen_ctrl_regs_ch6_pwidth_bits_o => pwidth_reg(6),
pgen_ctrl_regs_ch1_freq_bits_o => freq_reg(1),
pgen_ctrl_regs_ch2_freq_bits_o => freq_reg(2),
pgen_ctrl_regs_ch3_freq_bits_o => freq_reg(3),
pgen_ctrl_regs_ch4_freq_bits_o => freq_reg(4),
pgen_ctrl_regs_ch5_freq_bits_o => freq_reg(5),
pgen_ctrl_regs_ch6_freq_bits_o => freq_reg(6)
);
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
--============================================================================
-- Pulse generation logic
--============================================================================
-- First, the TTL trigger mux, selected via the TTL switch; ttlbar_nosig_n is
-- controlled in the process below
trig_ttl_a <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i;
-- Then, the blocking trigger
trig_blo_a <= fpga_blo_in_i;
-- And now the OR gate at the inputs of the pulse generator blocks
trig_a <= trig_ttl_a or trig_blo_a;
-----------------------------------------------------------------------------
-- Generate logic for each channel
-----------------------------------------------------------------------------
gen_chan_logic : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk20_vcxo_i domain
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i)
);
-- Instantiate output pulse generators
cmp_pulse_gen : pulse_gen_gp
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
en_i => ch_en(i),
delay_i => delay_reg(i),
pwidth_i => pwidth_reg(i),
freq_i => freq_reg(i),
pulse_o => pulse(i)
);
-- Delay reg for output pulses
p_delay_pulse : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
pulse_d0(i) <= '0';
pulse_r_edge_p(i) <= '0';
else
pulse_d0(i) <= pulse(i);
pulse_r_edge_p(i) <= pulse(i) and (not pulse_d0(i));
end if;
end if;
end process p_delay_pulse;
-- Pulse counting logic
p_cnt_pulses : process(clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') or (cntrst = '1') then
cnt_in(i) <= (others => '0');
cnt_out(i) <= (others => '0');
else
if (pulse_r_edge_p(i) = '1') then
cnt_out(i) <= cnt_out(i) + 1;
end if;
if (trig_synced_edge(i) = '1') then
cnt_in(i) <= cnt_in(i) + 1;
end if;
end if;
end if;
end process p_cnt_pulses;
-- Process to flash pulse LED on pulse reception
-- LED flash length: 26 ms
p_pulse_led : process (clk20_vcxo_i, rst_n) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
pulse_led_cnt(i) <= (others => '0');
pulse_leds(i) <= '0';
else
case pulse_leds(i) is
when '0' =>
if (pulse_r_edge_p(i) = '1') then
pulse_leds(i) <= '1';
end if;
when '1' =>
pulse_led_cnt(i) <= pulse_led_cnt(i) + 1;
if (pulse_led_cnt(i) = (pulse_led_cnt(i)'range => '1')) then
pulse_leds(i) <= '0';
end if;
when others =>
pulse_leds(i) <= '0';
end case;
end if;
end if;
end process;
-- Set the pulse status LED for the channel
pulse_front_led_n_o(i) <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
pulse_rear_led_n_o(i) <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
end generate gen_chan_logic;
-----------------------------------------------------------------------------
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse when (ttl_switch_n_i = '0') else
not pulse;
fpga_trig_blo_o <= pulse; --(others => '0');
--============================================================================
-- Pulse counter registers instantiation
--============================================================================
cmp_pulse_cnt_regs : pulse_cnt_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk20_vcxo_i,
wb_adr_i => xbar_master_out(c_slv_pulse_cnt).adr(5 downto 2),
wb_dat_i => xbar_master_out(c_slv_pulse_cnt).dat,
wb_dat_o => xbar_master_in(c_slv_pulse_cnt).dat,
wb_cyc_i => xbar_master_out(c_slv_pulse_cnt).cyc,
wb_sel_i => xbar_master_out(c_slv_pulse_cnt).sel,
wb_stb_i => xbar_master_out(c_slv_pulse_cnt).stb,
wb_we_i => xbar_master_out(c_slv_pulse_cnt).we,
wb_ack_o => xbar_master_in(c_slv_pulse_cnt).ack,
wb_stall_o => xbar_master_in(c_slv_pulse_cnt).stall,
pulse_cnt_ch1i_val_i => std_logic_vector(cnt_in(1)),
pulse_cnt_ch1o_val_i => std_logic_vector(cnt_out(1)),
pulse_cnt_ch2i_val_i => std_logic_vector(cnt_in(2)),
pulse_cnt_ch2o_val_i => std_logic_vector(cnt_out(2)),
pulse_cnt_ch3i_val_i => std_logic_vector(cnt_in(3)),
pulse_cnt_ch3o_val_i => std_logic_vector(cnt_out(3)),
pulse_cnt_ch4i_val_i => std_logic_vector(cnt_in(4)),
pulse_cnt_ch4o_val_i => std_logic_vector(cnt_out(4)),
pulse_cnt_ch5i_val_i => std_logic_vector(cnt_in(5)),
pulse_cnt_ch5o_val_i => std_logic_vector(cnt_out(5)),
pulse_cnt_ch6i_val_i => std_logic_vector(cnt_in(6)),
pulse_cnt_ch6o_val_i => std_logic_vector(cnt_out(6)),
pulse_cnt_rst_bit_o => cntrst
);
--============================================================================
-- Inverter outputs assignment
--============================================================================
inv_out_o <= inv_in_n_i;
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in(c_slv_multiboot).int <= '0';
xbar_master_in(c_slv_multiboot).rty <= '0';
xbar_master_in(c_slv_multiboot).err <= '0';
cmp_multiboot : wb_xil_multiboot
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (led_i2c_err = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (ttl_switch_n_i = '0') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm <= not fpga_rtmm_n_i;
rtmp <= not fpga_rtmp_n_i;
cmp_rtm_detector : rtm_detector
port map
(
rtmm_i => rtmm,
rtmp_i => rtmp,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- Theremometer output to high-impedance
thermometer_b <= 'Z';
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o <= '1';
fpga_plldac1_din_o <= '0';
fpga_plldac1_sclk_o <= '0';
fpga_plldac2_sync_n_o <= '1';
fpga_plldac2_din_o <= '0';
fpga_plldac2_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
fpga_sfp_rate_select_o <= 'Z';
fpga_sfp_mod_def1_b <= 'Z';
fpga_sfp_mod_def2_b <= 'Z';
fpga_sfp_tx_disable_o <= 'Z';
end behav;
--==============================================================================
-- architecture end
--==============================================================================
top/regtest/Manifest.py deleted 100644 → 0
View file @ 68e5ac71
files = [
"regtest.ucf",
"regtest.vhd"
]
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../modules/"
],
}
top/regtest/regtest.ucf deleted 100644 → 0
View file @ 68e5ac71
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = LVCMOS33;
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- WHITE RABBIT
##=============================================================================
##-----------------------------------------------------------------------------
##-- Thermo for UID
##-----------------------------------------------------------------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- DAC control
##-----------------------------------------------------------------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- SFP connection
##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = LVCMOS33;
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
top/regtest/regtest.vhd deleted 100644 → 0
View file @ 68e5ac71
--==============================================================================
-- CERN (BE-CO-HT)
-- Long-term register test for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description:
-- This is the top-level file for the register test for TTL pulse converter
-- boards. It instantiates a single-port RAM from the general-cores OHWR
-- repository and connects this RAM via an xwb_crossbar (also from
-- general-cores) to the i2c_bridge component.
--
-- An external program on the PC should send commands according to the I2C
-- protocol established with ELMA [2], to write and read from the single-port
-- RAM. The CONV-TTL-BLO is plugged into this ELMA crate. The wb_i2c_bridge
-- translates these commands into wishbone accesses to the RAM.
--
-- An example program can be found in the conv-ttl-blo repository [3], under
-- the software/regtest/ folder. This Python script writes to and reads back
-- all data from the RAM and checks for correct reading.
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
-- [3] CONV-TTL-BLO project repository on OHWR,
-- http://www.ohwr.org/projects/conv-ttl-blo/repository
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity regtest is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clocks
-- 20 MHz from VCXO
clk20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end regtest;
architecture behav of regtest is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 1;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- MEM [000-FFF]
-----------------------------------------
-- slave order definitions
constant c_slv_mem : natural := 0;
-- base address definitions
constant c_addr_mem : t_wishbone_address := x"00000000";
-- address mask definitions
constant c_mask_mem : t_wishbone_address := x"00000000";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_addr_mem
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_mask_mem
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
--============================================================================
-- Signal declarations
--============================================================================
-- Reset signals
signal rst_n : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals
signal ram_we : std_logic;
signal ram_ack : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals
signal i2c_tip : std_logic;
signal i2c_tip_d0 : std_logic;
signal i2c_err_p : std_logic;
signal i2c_up : std_logic;
signal i2c_wdto_p : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal led_i2c_err : std_logic;
signal led_i2c_blink : std_logic;
signal led_wdto : std_logic;
-- Transfer trigger for oscilloscope
signal trig_p : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk20_vcxo_i,
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : wb_i2c_bridge
port map
(
-- Clock, reset
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_oe_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_oe_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
led_i2c_blink <= '0';
else
case led_i2c_blink is
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
end if;
when others =>
led_i2c_blink <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_i2c_err <= '0';
elsif (i2c_err_p = '1') then
led_i2c_err <= '1';
end if;
end if;
end process p_i2c_err_led;
-- Process to light a LED in case of WDTO error
p_wdto_led : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_wdto <= '0';
elsif (i2c_wdto_p = '1') then
led_wdto <= '1';
end if;
end if;
end process p_wdto_led;
-- Pulse the first LEMO output on the card's front panel when a transfer is
-- finished. This is used to scope the bus in case of error
p_trig_oscilloscope : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
i2c_tip_d0 <= '0';
trig_p <= '0';
else
i2c_tip_d0 <= i2c_tip;
trig_p <= (not i2c_tip) and (i2c_tip_d0);
end if;
end if;
end process p_trig_oscilloscope;
fpga_out_ttl_o(1) <= trig_p;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk20_vcxo_i,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Instantiate single-port RAM
--============================================================================
cmp_memory: generic_spram
generic map (
g_data_width => 32,
g_size => 2**12
)
port map (
rst_n_i => rst_n,
clk_i => clk20_vcxo_i,
bwe_i => (others => '0'),
we_i => ram_we,
a_i => xbar_master_out(c_slv_mem).adr(11 downto 0),
d_i => xbar_master_out(c_slv_mem).dat,
q_o => xbar_master_in(c_slv_mem).dat
);
ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
xbar_master_out(c_slv_mem).cyc;
xbar_master_in(c_slv_mem).ack <= ram_ack;
xbar_master_in(c_slv_mem).err <= '0';
p_ram_ack : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
ram_ack <= '0';
else
ram_ack <= '0';
if (xbar_master_out(c_slv_mem).stb = '1') and
(xbar_master_out(c_slv_mem).cyc = '1') then
ram_ack <= '1';
end if;
end if;
end if;
end process p_ram_ack;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_RED when led_wdto = '1' else
c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (led_i2c_err = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- Theremometer output to high-impedance
thermometer_b <= 'Z';
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o <= '1';
fpga_plldac1_din_o <= '0';
fpga_plldac1_sclk_o <= '0';
fpga_plldac2_sync_n_o <= '1';
fpga_plldac2_din_o <= '0';
fpga_plldac2_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
fpga_sfp_rate_select_o <= 'Z';
fpga_sfp_mod_def1_b <= 'Z';
fpga_sfp_mod_def2_b <= 'Z';
fpga_sfp_tx_disable_o <= 'Z';
-- Pulse outputs and pulse LEDs
fpga_oe_o <= '1';
fpga_blo_oe_o <= '0';
fpga_trig_ttl_oe_o <= '1';
fpga_inv_oe_o <= '0';
pulse_front_led_n_o <= (others => '1');
pulse_rear_led_n_o <= (others => '1');
fpga_out_ttl_o(6 downto 2) <= (others => '0');
fpga_trig_blo_o <= (others => '0');
inv_out_o <= (others => '0');
-- Flash outputs
fpga_prom_cclk_o <= '0';
fpga_prom_cso_b_n_o <= '1';
fpga_prom_mosi_o <= '0';
end behav;
--==============================================================================
-- architecture end
--==============================================================================
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