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Conv TTL Blocking - Gateware
Commit 94931067 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Commented out the hack for v3 boards, where the PCB version is not yet… 

Commented out the hack for v3 boards, where the PCB version is not yet available. the previous top file was enabling the burst mode via a dip switch sw2.3. In final release this functionality is ONLY enabled by reading the PCB version inputs to the FPGA
parent 393015d1
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top/Release/conv_ttl_blo.vhd
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......@@ -334,20 +334,20 @@ begin
--Note that this burst mode functionality is activated only for PCB v4 or later
--The FPGA
-- Functionality enabled for versions 4 and above
--Burst mode functionality is enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
-- burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are able to
-- support v4 functionality
burst_en_n <= '0' when sw_gp_n_i(6)= '0'
else '1';
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are physically able to
-- support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--**************************************************************************
--**************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
......
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