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Conv TTL Blocking - Gateware
Commit 92c9d25a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Commented code, prior to merge with master branch 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent bfa6c70e
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Showing with 121 additions and 373 deletions
hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ 92c9d25a
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hdl/multiboot/rtl/multiboot_regs.vhd
View file @ 92c9d25a
......@@ -3,15 +3,16 @@
-- Wishbone registers for xil_multiboot design
--==============================================================================
--
-- author: auto-generated by wbgen2 from conv_regs.wb and modified by
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
--
-- description: Implements the control status and address registers and
-- Wishbone interface for the MultiBoot design.
-- description:
-- Implements the registers and Wishbone interface for the MultiBoot design.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
......@@ -53,33 +54,24 @@ entity multiboot_regs is
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
--multiboot_cr_flr_o : out std_logic;
--multiboot_cr_flw_o : out std_logic;
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
--multiboot_sr_flrrdy_i : in std_logic;
--multiboot_sr_flwrdy_i : in std_logic;
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
-- Fields of FAR register
--multiboot_far_data_load_o : out std_logic;
multiboot_far_data_i : in std_logic_vector(23 downto 0);
multiboot_far_data_o : out std_logic_vector(23 downto 0);
multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_cs_o : out std_logic;
multiboot_far_ready_i : in std_logic
---- Fields of bitstream address registers
--multiboot_flrdr_i : in std_logic_vector(31 downto 0);
--multiboot_flwdr_o : out std_logic_vector(31 downto 0)
multiboot_far_data_i : in std_logic_vector(23 downto 0);
multiboot_far_data_o : out std_logic_vector(23 downto 0);
multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_cs_o : out std_logic;
multiboot_far_ready_i : in std_logic
);
end multiboot_regs;
......@@ -118,11 +110,8 @@ begin
multiboot_sr_bootsts_img_int <= multiboot_sr_bootsts_img_i;
multiboot_sr_valid_int <= multiboot_sr_valid_i;
--multiboot_sr_flrrdy_int <= multiboot_sr_flrrdy_i;
--multiboot_sr_flwrdy_int <= multiboot_sr_flwrdy_i;
--multiboot_flrdr_int <= multiboot_flrdr_i;
multiboot_far_ready_int <= multiboot_far_ready_i;
multiboot_far_ready_int <= multiboot_far_ready_i;
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -134,12 +123,10 @@ begin
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_cr_iprog_unl_int <= '0';
--multiboot_cr_flr_int <= '0';
multiboot_gbbar_int <= (others => '0');
multiboot_mbbar_int <= (others => '0');
multiboot_far_nbytes_int <= "00";
multiboot_far_data_int <= (others => '0');
--multiboot_far_data_load_int <= '0';
multiboot_far_cs_int <= '0';
multiboot_far_xfer_int <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -148,10 +135,7 @@ begin
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
multiboot_cr_rdbootsts_int <= '0';
--multiboot_far_data_load_int <= '0';
multiboot_far_xfer_int <= '0';
--multiboot_cr_flr_int <= '0';
--multiboot_cr_flw_int <= '0';
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
......@@ -166,8 +150,6 @@ begin
if (multiboot_cr_iprog_unl_int = '1') then
multiboot_cr_iprog_int <= wrdata_reg(17);
end if;
--multiboot_cr_flr_int <= wrdata_reg(4);
--multiboot_cr_flw_int <= wrdata_reg(5);
end if;
rddata_reg(0) <= multiboot_cr_rdbootsts_int;
rddata_reg(1) <= 'X';
......@@ -175,8 +157,6 @@ begin
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
--rddata_reg(4) <= multiboot_cr_flr_int;
--rddata_reg(5) <= multiboot_cr_flw_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -210,8 +190,8 @@ begin
end if;
rddata_reg(15 downto 0) <= multiboot_sr_bootsts_img_int;
rddata_reg(16) <= multiboot_sr_valid_int;
rddata_reg(17) <= 'X'; --multiboot_sr_flrrdy_int;
rddata_reg(18) <= 'X'; --multiboot_sr_flwrdy_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
......@@ -243,11 +223,10 @@ begin
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
--multiboot_far_data_load_int <= '1';
multiboot_far_data_int <= wrdata_reg(23 downto 0);
multiboot_far_data_int <= wrdata_reg(23 downto 0);
multiboot_far_nbytes_int <= wrdata_reg(25 downto 24);
multiboot_far_xfer_int <= wrdata_reg(26);
multiboot_far_cs_int <= wrdata_reg(27);
multiboot_far_xfer_int <= wrdata_reg(26);
multiboot_far_cs_int <= wrdata_reg(27);
end if;
rddata_reg(23 downto 0) <= multiboot_far_data_i;
rddata_reg(25 downto 24) <= multiboot_far_nbytes_int;
......@@ -259,13 +238,6 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
-- when "101" =>
-- if (wb_we_i = '1') then
-- multiboot_flwdr_int <= wrdata_reg;
-- end if;
-- rddata_reg <= multiboot_flwdr_int;
-- ack_sreg(0) <= '1';
-- ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -279,28 +251,27 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Drive the stall line
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- Read BOOTSTS register
multiboot_cr_rdbootsts_o <= multiboot_cr_rdbootsts_int;
-- IPROG
multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
---- Flash read
-- multiboot_cr_flr_o <= multiboot_cr_flr_int;
---- Flash write
-- multiboot_cr_flw_o <= multiboot_cr_flw_int;
-- GBBAR
multiboot_gbbar_o <= multiboot_gbbar_int;
-- MBBAR
multiboot_mbbar_o <= multiboot_mbbar_int;
-- FAR outputs
multiboot_far_data_o <= multiboot_far_data_int; --wrdata_reg(23 downto 0);
multiboot_far_nbytes_o <= multiboot_far_nbytes_int;
--multiboot_far_data_load_o <= multiboot_far_data_load_int;
multiboot_far_xfer_o <= multiboot_far_xfer_int;
multiboot_far_cs_o <= multiboot_far_cs_int;
---- Flash data word
-- multiboot_flwdr_o <= multiboot_flwdr_int;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
hdl/multiboot/rtl/xil_multiboot.vhd
View file @ 92c9d25a
This diff is collapsed.
hdl/multiboot/syn/conv_ttl_blo.gise
View file @ 92c9d25a
......@@ -73,35 +73,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827603" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827603" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827603" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827603" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827603" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827603" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745655" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827603" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745675" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1381745655">
<transform xil_pn:end_ts="1381827621" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1381827603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -119,11 +119,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1381745675" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1381745675">
<transform xil_pn:end_ts="1381827621" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1381827621">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381745686" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1381745675">
<transform xil_pn:end_ts="1381827630" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1381827621">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -132,7 +132,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1381745744" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1381745686">
<transform xil_pn:end_ts="1381827703" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1381827630">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -145,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1381745799" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1381745744">
<transform xil_pn:end_ts="1381827756" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1381827703">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -159,7 +159,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1381745835" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1381745799">
<transform xil_pn:end_ts="1381827792" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1381827756">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -171,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1381745799" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381745788">
<transform xil_pn:end_ts="1381827756" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381827745">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/multiboot/top/conv_ttl_blo.vhd
View file @ 92c9d25a
......@@ -238,8 +238,8 @@ architecture behav of conv_ttl_blo is
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
......@@ -550,8 +550,8 @@ begin
clk_i => clk125,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
wb_i => xbar_master_out(c_slv_multiboot),
wb_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
......
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