Skip to content

C
Conv TTL Blocking - Gateware
Commit 8f476bcc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

Added I2C bridge to firmware, updated pulse & reset gens with enable inp

parent 6e85dbda
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 920 additions and 88 deletions
hdl/pulse_gen/rtl/pulse_gen.vhd 0 → 100644
View file @ 8f476bcc
--==============================================================================
-- CERN (BE-CO-HT)
-- Test module for old repeater boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end entity pulse_gen;
architecture behav of pulse_gen is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal freq_cnt : unsigned(f_log2_size(g_freq)-1 downto 0);
signal delay_cnt : unsigned(f_log2_size(g_delay)-1 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Delay logic
--============================================================================
gen_nodelay: if (g_delay = 0) generate
delay_en <= '0';
end generate gen_nodelay;
gen_delay: if (g_delay > 0) generate
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
elsif (en_i = '1') and (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = g_delay-1) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end process p_delay;
end generate gen_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
freq_cnt <= (others => '0');
pulse_o <= '0';
elsif (en_i = '1') and (delay_en = '0') then
freq_cnt <= freq_cnt + 1;
pulse_o <= '0';
if (freq_cnt < g_pwidth) then
pulse_o <= '1';
elsif (freq_cnt = g_freq-1) then
freq_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ 8f476bcc
......@@ -79,6 +79,9 @@ entity pulse_generator is
-- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
......@@ -180,7 +183,9 @@ begin
if (pulse_rst = '1') then
pulse_type1 <= '0';
elsif rising_edge(trig_i) then
pulse_type1 <= '1';
if (en_i = '1') then
pulse_type1 <= '1';
end if;
end if;
end process p_pulse_type1;
......@@ -192,7 +197,7 @@ begin
pulse_type1_d0 <= '0';
pulse_type1_d1 <= '0';
pulse_type1_d2 <= '0';
else
elsif (en_i = '1') then
pulse_type1_d0 <= pulse_type1;
pulse_type1_d1 <= pulse_type1_d0;
pulse_type1_d2 <= pulse_type1_d1;
......@@ -206,10 +211,11 @@ begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_type2 <= '0';
elsif (state = ST_PULSE_TYPE2) then
pulse_type2 <= '1';
else
elsif (en_i = '1') then
pulse_type2 <= '0';
if (state = ST_PULSE_TYPE2) then
pulse_type2 <= '1';
end if;
end if;
end if;
end process p_pulse_type2;
......@@ -241,7 +247,7 @@ begin
pulse_rst <= '1';
width_cnt <= (others => '0');
trig_degl_d0 <= '0';
else
elsif (en_i = '1') then
-- Deglitched trigger delay
trig_degl_d0 <= trig_degl;
......
hdl/release/rtl/Manifest.py 0 → 100644
View file @ 8f476bcc
files = [
"conv_regs.vhd"
];
hdl/release/rtl/conv_regs.vhd 0 → 100644
View file @ 8f476bcc
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Thu May 16 16:11:38 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal conv_regs_id_bits_int : std_logic_vector(31 downto 0);
signal conv_regs_cr_rst_unlock_int : std_logic ;
signal conv_regs_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
conv_regs_id_bits_int <= x"424C4F32";
conv_regs_cr_rst_unlock_int <= '0';
conv_regs_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(30);
if (conv_regs_cr_rst_unlock_int = '1') then
conv_regs_cr_rst_int <= wrdata_reg(31);
end if;
end if;
rddata_reg(30) <= conv_regs_cr_rst_unlock_int;
rddata_reg(31) <= conv_regs_cr_rst_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
conv_regs_id_bits_o <= conv_regs_id_bits_int;
-- Reset unlock bit
conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
-- Reset bit
conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/release/rtl/conv_regs.wb 0 → 100644
View file @ 8f476bcc
peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "conv_regs";
reg {
name = "Board ID register";
description = "Bits of ID register, defaulting to ASCII string of BLO2";
prefix = "id";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "Control register";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
description = "1 - unlock reset bit\
0 - lock reset bit";
type = BIT;
align = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reset bit";
prefix = "rst";
description = "1 - initiate logic reset\
0 - no reset";
type = BIT;
align = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/release/syn/Makefile
View file @ 8f476bcc
......@@ -38,11 +38,14 @@ CWD := $(shell pwd)
FILES := ../top/conv_ttl_blo_v2.ucf \
../top/conv_ttl_blo_v2.vhd \
../rtl/conv_regs.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../vme64x_i2c/rtl/i2c_slave.vhd \
../../vme64x_i2c/rtl/vme64x_i2c.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 8f476bcc
......@@ -72,36 +72,37 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993353" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993366" xil_pn:in_ck="-88236163103343582" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366993353">
<transform xil_pn:end_ts="1368794227" xil_pn:in_ck="6309703152952971517" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1368794212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
......@@ -117,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1366993366" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366993366">
<transform xil_pn:end_ts="1368794227" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1368794227">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366993375" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366993366">
<transform xil_pn:end_ts="1368794236" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1368794227">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -130,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1366993409" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366993375">
<transform xil_pn:end_ts="1368794274" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1368794236">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -143,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1366993444" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366993409">
<transform xil_pn:end_ts="1368794312" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1368794274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -157,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1366993465" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366993444">
<transform xil_pn:end_ts="1368794333" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1368794312">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1366993444" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366993434">
<transform xil_pn:end_ts="1368794312" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1368794301">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 8f476bcc
This diff is collapsed.
hdl/release/top/Manifest.py
View file @ 8f476bcc
......@@ -6,6 +6,8 @@ files = [
modules = {
"local" : [
"../../reset_gen",
"../rtl",
"../../vme64x_i2c",
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
......
hdl/release/top/conv_ttl_blo_v2.ucf
View file @ 8f476bcc
......@@ -253,49 +253,50 @@ NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
###=============================================================================
###-- VME CONNECTOR SIGNALS
###=============================================================================
###-----------------------------------------------------------------------------
###-- I2C lines
###-----------------------------------------------------------------------------
#NET "scl_i" LOC = F19;
#NET "scl_i" IOSTANDARD = LVCMOS33;
#NET "scl_o" LOC = E20;
#NET "scl_o" IOSTANDARD = LVCMOS33;
#NET "scl_o" DRIVE = 4;
#NET "scl_oe_o" LOC = H18;
#NET "scl_oe_o" IOSTANDARD = LVCMOS33;
#NET "scl_oe_o" DRIVE = 4;
## NET "scl_oe_o" PULLDOWN;
#NET "sda_i" LOC = G20;
#NET "sda_i" IOSTANDARD = LVCMOS33;
#NET "sda_o" LOC = F20;
#NET "sda_o" IOSTANDARD = LVCMOS33;
#NET "sda_o" SLEW = FAST;
#NET "sda_o" DRIVE = 4;
## NET "sda_o" PULLUP;
#NET "sda_oe_o" LOC = J19;
#NET "sda_oe_o" IOSTANDARD = LVCMOS33;
#NET "sda_oe_o" SLEW = FAST;
#NET "sda_oe_o" DRIVE = 4;
## NET "sda_oe_o" PULLDOWN;
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- Geographical Address
###-----------------------------------------------------------------------------
#NET "fpga_ga_i[0]" LOC = H20;
#NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
#NET "fpga_ga_i[1]" LOC = J20;
#NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
#NET "fpga_ga_i[2]" LOC = K19;
#NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
#NET "fpga_ga_i[3]" LOC = K20;
#NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
#NET "fpga_ga_i[4]" LOC = L19;
#NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
#NET "fpga_gap_i" LOC = H19;
#NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- ROM memory
###-----------------------------------------------------------------------------
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 8f476bcc
This diff is collapsed.
hdl/reset_gen/rtl/reset_gen.vhd
View file @ 8f476bcc
......@@ -54,6 +54,7 @@ entity reset_gen is
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end entity reset_gen;
......@@ -91,7 +92,10 @@ begin
p_rst_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (cnt_en = '1') then
if (rst_i = '1') then
cnt_en <= '1';
cnt <= (others => '0');
elsif (cnt_en = '1') then
rst_n_o <= '0';
cnt <= cnt + 1;
if (cnt = g_reset_time) then
......
hdl/vme64x_i2c/Manifest.py 0 → 100644
View file @ 8f476bcc
modules = {"local" : "rtl" }
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment