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Conv TTL Blocking - Gateware
Commit 8b49f3a1 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Changes relating to new commits in conv_common_gw

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conv-common-gw @ ba9673e5
Subproject commit 2a822c958e2671b35bfff33511fafb727190513d Subproject commit ba9673e5ed4717e36efae8d3f98755747e81c28e
sim/Release/burst_ctrl_tb.vhd
View file @ 8b49f3a1
...@@ -44,7 +44,7 @@ use ieee.math_real.all; ...@@ -44,7 +44,7 @@ use ieee.math_real.all;
use std.textio.all; use std.textio.all;
--use work.gencores_pkg.all; use work.gencores_pkg.all;
--use work.wishbone_pkg.all; --use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all; use work.conv_common_gw_pkg.all;
...@@ -76,6 +76,8 @@ architecture behav of testbench is ...@@ -76,6 +76,8 @@ architecture behav of testbench is
-- Enable input, pulse generation is enabled when '1' -- Enable input, pulse generation is enabled when '1'
en_i : in std_logic; en_i : in std_logic;
pulse_burst_i : in std_logic; pulse_burst_i : in std_logic;
pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic;
pulse_burst_o : out std_logic; pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives -- Burst error output, pulses high for one clock cycle when a pulse arrives
...@@ -93,8 +95,8 @@ architecture behav of testbench is ...@@ -93,8 +95,8 @@ architecture behav of testbench is
signal en : std_logic; signal en : std_logic;
signal burst_train : std_logic; signal burst_train : std_logic;
--signal burst_train_dyn : std_logic; signal burst_train_f_edge : std_logic;
signal burst_train_regulated : std_logic; signal burst_train_r_edge : std_logic;
signal burst_train_regulated_dyn : std_logic; signal burst_train_regulated_dyn : std_logic;
signal rand_num : integer := 0; signal rand_num : integer := 0;
...@@ -126,9 +128,9 @@ architecture behav of testbench is ...@@ -126,9 +128,9 @@ architecture behav of testbench is
g_temp_decre_step => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0), g_temp_decre_step => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_1_pulse_temp_rise => x"01388", g_1_pulse_temp_rise => x"01388",
--g_1_pulse_temp_rise => x"23040", -- for 1.2us pulse --g_1_pulse_temp_rise => x"23040", -- for 1.2us pulse
g_max_temp => x"00000F4240" --10^6 --g_max_temp => x"00000F4240" --10^6
--g_max_temp => x"02540BE400" --10^10 g_max_temp => x"02540BE400" --10^10
) )
port map( port map(
clk_i => clk_20, clk_i => clk_20,
...@@ -136,7 +138,8 @@ architecture behav of testbench is ...@@ -136,7 +138,8 @@ architecture behav of testbench is
en_i => en, en_i => en,
pulse_burst_i => burst_train, pulse_burst_i => burst_train,
pulse_r_edge_p_i => burst_train_r_edge,
pulse_f_edge_p_i => burst_train_f_edge,
pulse_burst_o => burst_train_regulated_dyn, pulse_burst_o => burst_train_regulated_dyn,
burst_err_p_o => open burst_err_p_o => open
...@@ -193,11 +196,26 @@ end process p_ran_gen; ...@@ -193,11 +196,26 @@ end process p_ran_gen;
-- Pulse stimuli -- Pulse stimuli
--============================================================================ --============================================================================
cmp_sync_input : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_20,
rst_n_i => rst,
data_i => burst_train,
npulse_o => burst_train_f_edge,
ppulse_o => burst_train_r_edge
);
p_stim_burst1 : process p_stim_burst1 : process
variable interval : time;-- := 1000 ns; variable interval : time;-- := 1000 ns;
begin begin
while t_sim1 < 50000 us loop while t_sim1 < 5000000 us loop
--while true loop --while true loop
t_sim1 <= NOW - t_start; t_sim1 <= NOW - t_start;
if random_intervals then if random_intervals then
...@@ -206,7 +224,7 @@ end process p_ran_gen; ...@@ -206,7 +224,7 @@ end process p_ran_gen;
interval := 250 ns; interval := 250 ns;
end if; end if;
else else
interval := 250 ns;--changes pulse frequency interval := 1500 ns;--changes pulse frequency
end if; end if;
burst_train <= '0'; burst_train <= '0';
wait for interval; wait for interval;
...@@ -215,19 +233,19 @@ end process p_ran_gen; ...@@ -215,19 +233,19 @@ end process p_ran_gen;
burst_train <= '0'; burst_train <= '0';
end loop; end loop;
while t_sim2 < 50000 us loop -- while t_sim2 < 50000 us loop
t_sim2 <= NOW - t_sim1; -- t_sim2 <= NOW - t_sim1;
if random_intervals then -- if random_intervals then
interval := rand_num * 1 ns; -- interval := rand_num * 1 ns;
else -- else
interval := 1750 ns; -- interval := 1750 ns;
end if; -- end if;
burst_train <= '0'; -- burst_train <= '0';
wait for interval; -- wait for interval;
burst_train <= '1'; -- burst_train <= '1';
wait for 250 ns; -- wait for 250 ns;
burst_train <= '0'; -- burst_train <= '0';
end loop; -- end loop;
end process p_stim_burst1; end process p_stim_burst1;
......
sim/Release/testbenchv4.vhd
View file @ 8b49f3a1
...@@ -383,7 +383,7 @@ begin ...@@ -383,7 +383,7 @@ begin
vme_ga_i => "11110", vme_ga_i => "11110",
vme_gap_i => '0', vme_gap_i => '0',
pcbrev_i => x"0", pcbrev_i => pcbversn,
-- Output enable lines -- Output enable lines
global_oen_o => oe, global_oen_o => oe,
...@@ -476,7 +476,7 @@ begin ...@@ -476,7 +476,7 @@ begin
--============================================================================ --============================================================================
pcbversn (3 downto 0) <= "0100"; --For version 4 pcbversn (3 downto 0) <= "0100"; --For version 4
pcbversn (3 downto 0) <= "0011"; --For version 3 --pcbversn (3 downto 0) <= "0011"; --For version 3
--============================================================================ --============================================================================
-- Switches -- Switches
--============================================================================ --============================================================================
...@@ -486,8 +486,8 @@ begin ...@@ -486,8 +486,8 @@ begin
-- GF -- GF
switches_n(0) <= '1'; switches_n(0) <= '1';
--burst mode is 0 else 1 for normal operation --burst mode is 0 for short pulses and 1 for long pulses
switches_n(1) <= '0'; switches_n(1) <= '1';
-- other -- other
......
top/Release/conv_ttl_blo.vhd
View file @ 8b49f3a1
...@@ -338,10 +338,13 @@ begin ...@@ -338,10 +338,13 @@ begin
--Note that this burst mode functionality is activated only for PCB ver 4 or later --Note that this burst mode functionality is activated only for PCB ver 4 or later
--The FPGA --The FPGA
burst_en_n <= '0' when pcbrev_i>="0100" --Functionality enabled for versions 4 and above
burst_en_n <= '0' when pcbrev_i >= "0100" --Functionality enabled for versions 4 and above
else '1'; --when version is below 4 then disable burst functionality else '1'; --when version is below 4 then disable burst functionality
--This change needs to be deleted for gw release, only used oas a hack for v3 boards
-- burst_en_n <= '0' when sw_gp(6 downto 3)>="0100" --Functionality enabled for versions 4 and above
-- else '1'; --when version is below 4 then disable burst functionality
--============================================================================ --============================================================================
-- Instantiate common generic gateware for converter boards -- Instantiate common generic gateware for converter boards
...@@ -366,8 +369,8 @@ begin ...@@ -366,8 +369,8 @@ begin
g_temp_decre_step_sh => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0), g_temp_decre_step_sh => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_burstctrl_1_pulse_temp_rise_lg => x"23040", g_burstctrl_1_pulse_temp_rise_lg => x"23040",
g_burstctrl_1_pulse_temp_rise_sh => x"01388", g_burstctrl_1_pulse_temp_rise_sh => x"01388",
--g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value g_burstctrl_max_temp_lg_sh=> x"02540BE400", -- 10^10 --In final release use this value
g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation --g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt => true, g_with_pulse_cnt => true,
g_with_pulse_timetag => true, g_with_pulse_timetag => true,
g_with_man_trig => true, g_with_man_trig => true,
......
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