hdl: Added manual pulse trigger module

Also renamed "ctb_pulse_gen" to "conv_pulse_gen" Signed-off-by: Theodor Stana <t.stana@cern.ch>

hdl: Added manual pulse trigger module
Also renamed "ctb_pulse_gen" to "conv_pulse_gen" Signed-off-by: Theodor Stana <t.stana@cern.ch>
83b87d10 · Theodor-Adrian Stana · 4c0dd945 · 83b87d10 · 83b87d10 · 83b87d10
Commit 83b87d10 authored Jan 29, 2014 by Theodor-Adrian Stana
12 changed files
--- a/doc/hdlguide/fig/hdl-bd.svg
+++ b/doc/hdlguide/fig/hdl-bd.svg
@@ -196,9 +196,9 @@
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@@ -780,7 +780,7 @@
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             style="font-weight:bold;text-align:start;text-anchor:start"
-             id="tspan13485">ctb_pulse_gen</tspan></text>
+             id="tspan13485">conv_pulse_gen</tspan></text>
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--- a/doc/hdlguide/hdlguide-conv-ttl-blo.tex
+++ b/doc/hdlguide/hdlguide-conv-ttl-blo.tex
@@ -55,7 +55,7 @@
  \hline
  04-07-2013 & 0.1 & First draft \\
  26-07-2013 & 0.2 & Second draft \\
-  07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
+  07-08-2013 & 1.02 & Added pulse rejection to \textit{conv\_pulse\_gen} \\
  14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\
  29-10-2013 & 1.03 & Added MultiBoot support to gateware \\
  20-11-2013 & 1.04 & Changed system clock to 20~MHz \\
@@ -396,7 +396,7 @@ selection signals to these multiplexers are set throughout the logic.
  {
    \begin{tabular}{l l l}
    \hline
-    \textbf{Entity} & \textit{ctb\_pulse\_gen} & \\
+    \textbf{Entity} & \textit{conv\_pulse\_gen} & \\
    \textbf{Generics} & \textit{g\_pwidth}     & Width of the output pulse in \textit{clk\_i} cycles \\
                      & \textit{g\_gf\_len}    & Length of glitch filter in \textit{clk\_i} cycles \\
    \textbf{Ports} & \textit{clk\_i}           & Clock signal \\
@@ -413,7 +413,7 @@ selection signals to these multiplexers are set throughout the logic.
 \vspace*{11pt}
-The \textit{ctb\_pulse\_gen} block generates pulses on the rising edge of the
+The \textit{conv\_pulse\_gen} block generates pulses on the rising edge of the
 \textit{trig\_i} input. The pulse width is configurable via the \textit{g\_pwidth}
 generic. The block also incorporates a glitch filter with a configurable length
 (\textit{g\_gf\_len}) that can be used to avoid pulses generated because of
@@ -422,8 +422,8 @@ glitches at the \textit{trig\_i} input.
 Pulse widths at the output are limited internally to 1/5 duty cycle, to safeguard
 the blocking output transformers.
-Six \textit{ctb\_pulse\_gen} blocks (one per channel) are used for generating blocking and TTL
+Six \textit{conv\_pulse\_gen} blocks (one per channel) are used for generating blocking and TTL
-pulses at the outputs, based on trigger inputs arriving on the channels. The \textit{ctb\_pulse\_gen} blocks
+pulses at the outputs, based on trigger inputs arriving on the channels. The \textit{conv\_pulse\_gen} blocks
 are configured for 1.2~${\mu}$s pulses (\textit{g\_pwidth~=~24}, considering the 50~ns clock input).
 %------------------------------------------------------------------------------
@@ -432,7 +432,7 @@ are configured for 1.2~${\mu}$s pulses (\textit{g\_pwidth~=~24}, considering the
 \subsection{Implementation}
 \label{sec:pulse-gen-implem}
-Figure~\ref{fig:pulse-gen} shows the implementation of the \textit{ctb\_pulse\_gen}
+Figure~\ref{fig:pulse-gen} shows the implementation of the \textit{conv\_pulse\_gen}
 block. It employs a finite-state machine (FSM) that is used to generate
 a fixed-width pulse at the output.
@@ -485,8 +485,8 @@ in the code. These constants assure the pulse at the output is kept high for a n
 \label{sec:pulse-gen-brdlvl}
 Figure~\ref{fig:pulse-brd} shows the pulse replication mechanism on the
-CONV-TTL-BLO. Here, the \textit{PG} block is the \textit{ctb\_pulse\_gen} block
+CONV-TTL-BLO. Here, the \textit{PG} block is the \textit{conv\_pulse\_gen} block
-with the necessary settings. Since the \textit{ctb\_pulse\_gen} block expects
+with the necessary settings. Since the \textit{conv\_pulse\_gen} block expects
 a rising edge at its \textit{trig\_i} input in order to generate a pulse at
 the output, logic external to the block caters for the different types of signals
 that arrive on CONV-TTL-BLO inputs.
@@ -673,7 +673,7 @@ The folder structure for the project is presented below.
        \item pulse\_gen\_gp.vhd
        \item {[}...{]}
      \end{itemize}
-      \item ctb\_pulse\_gen.vhd
+      \item conv\_pulse\_gen.vhd
      \item reset\_gen.vhd
      \item rtm\_detector.vhd
    \end{itemize}
@@ -807,7 +807,7 @@ top-level file.
                    -- synchronization flip-flops on the input signals \newline
                    -- input pulse counter logic \newline
                    -- no signal detect block (Figure~\ref{fig:no-sig-detect}) \newline
-                    -- \textit{ctb\_pulse\_gen} instantiation \newline
+                    -- \textit{conv\_pulse\_gen} instantiation \newline
                    -- pulse output connections \newline
                    -- process to light pulse LEDs on pulse output \\
    MultiBoot logic & -- \textit{wb\_xil\_multiboot} instantiation \\
@@ -1192,7 +1192,9 @@ $reg. index = \frac{addr}{4} + 1$
  \end{tabular}
 }
+%------------------------------------------------------------------------------
 \end{appendices}
+%------------------------------------------------------------------------------
 %==============================================================================
 % Bibliography

--- a/modules/Manifest.py
+++ b/modules/Manifest.py
@@ -7,7 +7,7 @@ modules = {
    }
 files = [
-      "ctb_pulse_gen.vhd",
+      "conv_pulse_gen.vhd",
      "reset_gen.vhd",
      "rtm_detector.vhd"
    ]
--- a/modules/Release/Manifest.py
+++ b/modules/Release/Manifest.py
 files = [
-      "conv_regs.vhd"
+      "conv_regs.vhd",
+      "conv_man_trig.vhd"
    ];
--- a/modules/Release/conv_man_trig.vhd
+++ b/modules/Release/conv_man_trig.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Pulse trigger for pulse converter boards
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2014-01-28
+--
+-- version: 1.0
+--
+-- description:
+--
+-- dependencies:
+--      genram_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
+--
+-- references:
+--
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2014-01-28   Theodor Stana     File created
+--==============================================================================
+-- TODO: -
+--==============================================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.genram_pkg.all;
+entity conv_man_trig is
+  generic
+  (
+    -- Number of conversion channels
+    g_nr_chan : positive := 6
+  );
+  port
+  (
+    -- Clock, active-low inputs
+    clk_i     : in  std_logic;
+    rst_n_i   : in  std_logic;
+    -- Control inputs from conv_regs
+    reg_ld_i : in  std_logic;
+    reg_i    : in  std_logic_vector(7 downto 0);
+    -- One-clock pulse output
+    p_o       : out std_logic_vector(g_nr_chan downto 1)
+  );
+end entity conv_man_trig;
+architecture behav of conv_man_trig is
+  --============================================================================
+  -- Type declarations
+  --============================================================================
+  -- Type for the "password" array
+  type t_pass_arr is array(integer range <>) of std_logic_vector(7 downto 0);
+  -- FSM type
+  type t_state is
+    (
+      IDLE,
+      PASS1,
+      PASS2,
+      PASS3,
+      GEN
+    );
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  constant c_pass_arr : t_pass_arr(0 to 3) := (x"de", x"ad", x"be", x"ef");
+  --============================================================================
+  -- Function and procedures declaration
+  --============================================================================
+  procedure f_change_state (
+    signal   ld     : in  std_logic;
+    signal   pass   : in  std_logic_vector(7 downto 0);
+    constant idx    : in  integer;
+    signal   state  : out t_state;
+    constant nstate : in  t_state
+  ) is
+  begin
+    if (ld = '1') then
+      if (pass = c_pass_arr(idx)) then
+        state <= nstate;
+      else
+        state <= IDLE;
+      end if;
+    end if;
+  end procedure f_change_state;
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  -- Signal for the current state of the FSM
+  signal state : t_state;
+  -- "Password" and channel number signals
+  signal pass  : std_logic_vector(7 downto 0);
+  signal chnr  : std_logic_vector(f_log2_size(g_nr_chan)-1 downto 0);
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+  --============================================================================
+  -- FSM logic
+  --============================================================================
+  -- First, assign the password, channel enable and channel number signals
+  pass <= reg_i;
+  chnr <= reg_i(f_log2_size(g_nr_chan)-1 downto 0);
+  -- Then, the process for the FSM
+  p_fsm : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+        state <= IDLE;
+        p_o   <= (others => '0');
+      else
+        case state is
+          when IDLE =>
+            p_o <= (others => '0');
+            f_change_state(reg_ld_i, pass, 0, state, PASS1);
+          when PASS1 =>
+            f_change_state(reg_ld_i, pass, 1, state, PASS2);
+          when PASS2 =>
+            f_change_state(reg_ld_i, pass, 2, state, PASS3);
+          when PASS3 =>
+            f_change_state(reg_ld_i, pass, 3, state, GEN);
+          when GEN =>
+            if (reg_ld_i = '1') then
+              p_o(to_integer(unsigned(chnr))) <= '1';
+              state <= IDLE;
+            end if;
+          when others =>
+            state <= IDLE;
+        end case;
+      end if;
+    end if;
+  end process p_fsm;
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/modules/Release/conv_regs.vhd
+++ b/modules/Release/conv_regs.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : conv_regs.vhd
 -- Author         : auto-generated by wbgen2 from conv_regs.wb
-- Created        : Mon Jan 27 15:46:19 2014
+-- Created        : Tue Jan 28 16:42:43 2014
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
@@ -47,6 +47,9 @@ entity conv_regs is
    reg_cr_rst_o                             : out    std_logic;
    reg_cr_rst_i                             : in     std_logic;
    reg_cr_rst_load_o                        : out    std_logic;
+-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'Control Register'
+    reg_cr_mpt_o                             : out    std_logic_vector(7 downto 0);
+    reg_cr_mpt_wr_o                          : out    std_logic;
 -- Port for std_logic_vector field: 'bits' in reg: 'CH1 Pulse Counter Register'
    reg_ch1pcr_o                             : out    std_logic_vector(31 downto 0);
    reg_ch1pcr_i                             : in     std_logic_vector(31 downto 0);
@@ -106,6 +109,7 @@ begin
      reg_sr_i2c_wdto_load_o <= '0';
      reg_cr_rst_unlock_load_o <= '0';
      reg_cr_rst_load_o <= '0';
+      reg_cr_mpt_wr_o <= '0';
      reg_ch1pcr_load_o <= '0';
      reg_ch2pcr_load_o <= '0';
      reg_ch3pcr_load_o <= '0';
@@ -121,6 +125,7 @@ begin
          reg_sr_i2c_wdto_load_o <= '0';
          reg_cr_rst_unlock_load_o <= '0';
          reg_cr_rst_load_o <= '0';
+          reg_cr_mpt_wr_o <= '0';
          reg_ch1pcr_load_o <= '0';
          reg_ch2pcr_load_o <= '0';
          reg_ch3pcr_load_o <= '0';
@@ -132,6 +137,7 @@ begin
          reg_sr_i2c_wdto_load_o <= '0';
          reg_cr_rst_unlock_load_o <= '0';
          reg_cr_rst_load_o <= '0';
+          reg_cr_mpt_wr_o <= '0';
          reg_ch1pcr_load_o <= '0';
          reg_ch2pcr_load_o <= '0';
          reg_ch3pcr_load_o <= '0';
@@ -171,6 +177,7 @@ begin
            if (wb_we_i = '1') then
              reg_cr_rst_unlock_load_o <= '1';
              reg_cr_rst_load_o <= '1';
+              reg_cr_mpt_wr_o <= '1';
            end if;
            rddata_reg(0) <= reg_cr_rst_unlock_i;
            rddata_reg(1) <= reg_cr_rst_i;
@@ -271,6 +278,9 @@ begin
  reg_cr_rst_unlock_o <= wrdata_reg(0);
 -- Reset bit
  reg_cr_rst_o <= wrdata_reg(1);
+-- Manual Pulse Trigger
+-- pass-through field: Manual Pulse Trigger in register: Control Register
+  reg_cr_mpt_o <= wrdata_reg(9 downto 2);
 -- bits
  reg_ch1pcr_o <= wrdata_reg(31 downto 0);
 -- bits

--- a/modules/Release/conv_regs.wb
+++ b/modules/Release/conv_regs.wb
@@ -130,6 +130,12 @@ peripheral {
      access_dev = READ_WRITE;
      load = LOAD_EXT;
    };
+    field {
+      name = "Manual Pulse Trigger";
+      prefix = "mpt";
+      size = 8;
+      type = PASS_THROUGH;
+    };
  };
  -- Pulse counter registers, R/W access from SysMon

--- a/modules/ctb_pulse_gen.vhd
+++ b/modules/ctb_pulse_gen.vhd
@@ -58,7 +58,7 @@ use ieee.numeric_std.all;
 use work.gencores_pkg.all;
-entity ctb_pulse_gen is
+entity conv_pulse_gen is
  generic
  (
    -- Pulse width, in number of clk_i cycles
@@ -97,10 +97,10 @@ entity ctb_pulse_gen is
    --    glitch filter enabled: g_gf_len+5 clk_i cycles
    pulse_o   : out std_logic
  );
-end entity ctb_pulse_gen;
+end entity conv_pulse_gen;
-architecture behav of ctb_pulse_gen is
+architecture behav of conv_pulse_gen is
  --============================================================================
  -- Type declarations

--- a/syn/Release/Makefile
+++ b/syn/Release/Makefile
@@ -39,7 +39,8 @@ CWD := $(shell pwd)
 FILES := ../../top/Release/conv_ttl_blo.ucf \
 ../../top/Release/conv_ttl_blo.vhd \
 ../../modules/Release/conv_regs.vhd \
-../../modules/ctb_pulse_gen.vhd \
+../../modules/Release/conv_man_trig.vhd \
+../../modules/conv_pulse_gen.vhd \
 ../../modules/reset_gen.vhd \
 ../../modules/rtm_detector.vhd \
 ../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
@@ -53,12 +54,14 @@ FILES := ../../top/Release/conv_ttl_blo.ucf \
 ../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
 ../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
 ../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
 ../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
 ../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
 ../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
 ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
 ../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
 ../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
+../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
 ../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
 ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
 ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
@@ -109,6 +112,8 @@ FILES := ../../top/Release/conv_ttl_blo.ucf \
 ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
 ../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \

--- a/syn/Release/conv_ttl_blo.xise
+++ b/syn/Release/conv_ttl_blo.xise
--- a/top/Release/conv_ttl_blo.ucf
+++ b/top/Release/conv_ttl_blo.ucf
@@ -453,4 +453,4 @@ NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
 # NET "fpga_header_in_n_i[5]"     IOSTANDARD = "LVCMOS33";
 # NET "fpga_header_in_n_i[6]"     LOC = B20;
 # NET "fpga_header_in_n_i[6]"     IOSTANDARD = "LVCMOS33";
+#
--- a/top/Release/conv_ttl_blo.vhd
+++ b/top/Release/conv_ttl_blo.vhd
@@ -167,15 +167,15 @@ architecture behav of conv_ttl_blo is
  -- Board ID - ASCII string "TBLO"
  constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-  -- Firmware version
+  -- Gateware version
  --    - format: M.m
  --    - M: major version hex number (e.g.  1)
  --    - m: minor version hex number (e.g. 13)
-  --    - example: first major release      v1.0  c_fwvers = x"10";
+  --    - example: first major release      v1.0  c_gwvers = x"10";
-  --               next minor release       v1.1  c_fwvers = x"11";
+  --               next minor release       v1.1  c_gwvers = x"11";
-  --               13 minor releases later  v1.14 c_fwvers = x"1e";
+  --               13 minor releases later  v1.14 c_gwvers = x"1e";
-  --               next major release       v2.0  c_fwvers = x"20";
+  --               next major release       v2.0  c_gwvers = x"20";
-  constant c_fwvers          : std_logic_vector(7 downto 0) := x"11";
+  constant c_gwvers          : std_logic_vector(7 downto 0) := x"12";
  -- Number of Wishbone masters and slaves, for wb_crossbar
  constant c_nr_masters      : natural :=  1;
@@ -198,8 +198,8 @@ architecture behav of conv_ttl_blo is
  constant c_addr_multiboot : t_wishbone_address := x"00000040";
  -- address mask definitions
-  constant c_mask_conv_regs : t_wishbone_address := x"00000FC0";
+  constant c_mask_conv_regs : t_wishbone_address := x"00000fc0";
-  constant c_mask_multiboot : t_wishbone_address := x"00000FC0";
+  constant c_mask_multiboot : t_wishbone_address := x"00000fc0";
  -- addresses constant for Wishbone crossbar
  constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
@@ -236,7 +236,7 @@ architecture behav of conv_ttl_blo is
  -- Pulse generator component
  -- (use: output pulse generation, pulse status LEDs)
-  component ctb_pulse_gen is
+  component conv_pulse_gen is
    generic
    (
      -- Pulse width, in number of clk_i cycles
@@ -275,7 +275,7 @@ architecture behav of conv_ttl_blo is
      --    glitch filter enabled: g_gf_len+5 clk_i cycles
      pulse_o   : out std_logic
    );
-  end component ctb_pulse_gen;
+  end component conv_pulse_gen;
  -- RTM detector component
  -- (use: detect the presence of an RTM/P module)
@@ -323,6 +323,9 @@ architecture behav of conv_ttl_blo is
      reg_cr_rst_o                             : out    std_logic;
      reg_cr_rst_i                             : in     std_logic;
      reg_cr_rst_load_o                        : out    std_logic;
+  -- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'Control Register'
+      reg_cr_mpt_o                             : out    std_logic_vector(7 downto 0);
+      reg_cr_mpt_wr_o                          : out    std_logic;
  -- Port for std_logic_vector field: 'bits' in reg: 'CH1 Pulse Counter Register'
      reg_ch1pcr_o                             : out    std_logic_vector(31 downto 0);
      reg_ch1pcr_i                             : in     std_logic_vector(31 downto 0);
@@ -371,6 +374,28 @@ architecture behav of conv_ttl_blo is
    );
  end component wb_xil_multiboot;
+  -- Manual pulse trigger component
+  component conv_man_trig is
+    generic
+    (
+      -- Number of conversion channels
+      g_nr_chan : positive := 6
+    );
+    port
+    (
+      -- Clock, active-low inputs
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+      -- Control inputs from conv_regs
+      reg_ld_i : in  std_logic;
+      reg_i    : in  std_logic_vector(7 downto 0);
+      -- One-clock pulse output
+      p_o      : out std_logic_vector(g_nr_chan downto 1)
+    );
+  end component conv_man_trig;
  --============================================================================
  -- Signal declarations
  --============================================================================
@@ -396,14 +421,17 @@ architecture behav of conv_ttl_blo is
  signal pulse_cnt            : t_pulse_cnt;
  signal ch_pcr               : t_ch_pcr;
  signal ch_pcr_ld            : std_logic_vector(g_nr_ttl_chan downto 1);
+  signal mpt_ld               : std_logic;
+  signal mpt                  : std_logic_vector(7 downto 0);
  -- Signals for pulse generation triggers
  signal trig_a               : std_logic_vector(g_nr_ttl_chan downto 1);
-  signal trig_inv             : std_logic_vector(g_nr_inv_chan downto 1);
  signal trig_ttl_a           : std_logic_vector(g_nr_ttl_chan downto 1);
  signal trig_blo_a           : std_logic_vector(g_nr_ttl_chan downto 1);
  signal trig_synced_r_edge_p : std_logic_vector(g_nr_ttl_chan downto 1);
  signal trig_synced          : std_logic_vector(g_nr_ttl_chan downto 1);
+  signal trig                 : std_logic_vector(g_nr_ttl_chan downto 1);
+  signal trig_man             : std_logic_vector(g_nr_ttl_chan downto 1);
  -- TTL-BAR lack of signal counter
  signal ttlbar_nosig_cnt     : t_ttlbar_nosig_cnt;
@@ -626,7 +654,7 @@ begin
      wb_stall_o               => xbar_master_in (c_slv_conv_regs).stall,
      reg_id_bits_i            => c_board_id,
-      reg_sr_fwvers_i          => c_fwvers,
+      reg_sr_fwvers_i          => c_gwvers,
      reg_sr_switches_i        => switches_n,
      reg_sr_rtm_i             => rtm_lines,
      reg_sr_i2c_wdto_o        => wdto_bit_rst,
@@ -638,6 +666,8 @@ begin
      reg_cr_rst_o             => rst_bit,
      reg_cr_rst_i             => rst_fr_reg,
      reg_cr_rst_load_o        => rst_bit_ld,
+      reg_cr_mpt_o             => mpt,
+      reg_cr_mpt_wr_o          => mpt_ld,
      reg_ch1pcr_o             => ch_pcr(1),
      reg_ch1pcr_i             => std_logic_vector(pulse_cnt(1)),
@@ -730,8 +760,29 @@ begin
  -- Then, the blocking trigger
  trig_blo_a <= fpga_blo_in_i;
+  -- Now, instantiate the manual pulse trigger component
+  cmp_man_trig : conv_man_trig
+    generic map
+    (
+      g_nr_chan => g_nr_ttl_chan
+    )
+    port map
+    (
+      -- Clock, active-low inputs
+      clk_i    => clk20_vcxo_i,
+      rst_n_i  => rst_n,
+      -- Control inputs from conv_regs
+      reg_ld_i => mpt_ld,
+      reg_i    => mpt,
+      -- One-clock pulse output
+      p_o      => trig_man
+    );
  -- And now the OR gate at the inputs of the pulse generator blocks
-  trig_a     <= trig_ttl_a or trig_blo_a;
+  trig_a <= trig_ttl_a or trig_blo_a;
+  trig   <= trig_a or trig_man;
  -----------------------------------------------------------------------------
  -- Generate pulse repetition logic
@@ -783,14 +834,19 @@ begin
    end process p_ttlbar_nosig;
    -- Output pulse generators
-    cmp_ttl_pulse_gen : ctb_pulse_gen
+    cmp_ttl_pulse_gen : conv_pulse_gen
+      generic map
+      (
+        g_pwidth  => 24,
+        g_gf_len  => 1
+      )
      port map
      (
        clk_i     => clk20_vcxo_i,
        rst_n_i   => rst_n,
        en_i      => '1',
        gf_en_n_i => extra_switch_n_i(1),
-        trig_a_i  => trig_a(i),
+        trig_a_i  => trig(i),
        pulse_o   => pulse_outp(i)
      );
@@ -837,9 +893,7 @@ begin
  pulse_rear_led_n_o  <= (not pulse_leds) when (blo_oe = '1') else
                         (others => '1');
-  --============================================================================
  -- General-purpose INV TTL outputs
-  --============================================================================
  inv_out_o <= inv_in_n_i;
  --============================================================================