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Conv TTL Blocking - Gateware
Commit 81fb2371 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Changed system clock from 125MHz to 20MHz VCXO 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 4e7feccb
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doc/hdlguide/fig/no-sig-detect.svg
View file @ 81fb2371
...@@ -238,13 +238,13 @@ ...@@ -238,13 +238,13 @@
sodipodi:linespacing="125%" sodipodi:linespacing="125%"
id="text3010" id="text3010"
y="157.67714" y="157.67714"
x="186.83545" x="207.69482"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan xml:space="preserve"><tspan
y="157.67714" y="157.67714"
x="186.83545" x="207.69482"
id="tspan3012" id="tspan3012"
sodipodi:role="line" sodipodi:role="line"
style="font-size:12px;font-weight:bold">12499</tspan></text> style="font-size:12px;font-weight:bold;text-align:center;text-anchor:middle">1999</tspan></text>
</g> </g>
</svg> </svg>
doc/hdlguide/hdlguide-conv-ttl-blo.tex
View file @ 81fb2371
...@@ -53,7 +53,8 @@ ...@@ -53,7 +53,8 @@
26-07-2013 & 0.2 & Second draft \\ 26-07-2013 & 0.2 & Second draft \\
07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\ 07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\ 14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\
29-10-2013 & 2.00 & Added MultiBoot support to firmware \\ 29-10-2013 & 1.03 & Added MultiBoot support to firmware \\
20-11-2013 & 1.04 & Changed system clock to 20~MHz \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -154,7 +155,7 @@ Table~\ref{tbl:clocks} lists the clock domains in the firmware. ...@@ -154,7 +155,7 @@ Table~\ref{tbl:clocks} lists the clock domains in the firmware.
\hline \hline
\textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\ \textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline \hline
\textit{clk125} & 125~MHz & Global clock input to all sequential logic \\ \textit{clk20\_vcxo\_i} & 20~MHz & Global clock input to all sequential logic \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -178,7 +179,7 @@ Table~\ref{tbl:clocks} lists the clock domains in the firmware. ...@@ -178,7 +179,7 @@ Table~\ref{tbl:clocks} lists the clock domains in the firmware.
\textbf{Ports} & \textit{clk\_i} & Clock signal \\ \textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_i} & Active-high reset input \\ & \textit{rst\_i} & Active-high reset input \\
& \textit{rst\_n\_o} & Active-low reset output \\ & \textit{rst\_n\_o} & Active-low reset output \\
\textbf{Usage} & Global reset generation & 96~$ms$ reset \\ \textbf{Usage} & Global reset generation & 100~$ms$ reset \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -193,8 +194,8 @@ when an external reset is triggered via the \textit{rst\_i} pin. ...@@ -193,8 +194,8 @@ when an external reset is triggered via the \textit{rst\_i} pin.
When a power-on reset occurs on the Xilinx FPGA, a counter inside the \textit{reset\_gen} When a power-on reset occurs on the Xilinx FPGA, a counter inside the \textit{reset\_gen}
module starts counting up. While this counter is counting up, the active-low reset signal module starts counting up. While this counter is counting up, the active-low reset signal
is kept low, resetting synchronous logic inside the FPGA. When the counter reaches the is kept low, resetting synchronous logic inside the FPGA. When the counter reaches the
value of the reset width (specified via the \textit{g\_reset\_time} generic at synthesis value of the reset width (specified via the \textit{g\_reset\_time} generic), the reset
time), the reset signal is de-asserted, the counter is disabled and the \textit{reset\_gen} signal is de-asserted, the counter is disabled and the \textit{reset\_gen}
module remains inactive. module remains inactive.
The module reactivates on the power-on reset, or when a reset is triggered externally, via The module reactivates on the power-on reset, or when a reset is triggered externally, via
...@@ -205,7 +206,7 @@ FPGA architecture is not guaranteed to provide the same results. The \textit{res ...@@ -205,7 +206,7 @@ FPGA architecture is not guaranteed to provide the same results. The \textit{res
module has an initial value set for the counter signal after power-up, which is guaranteed module has an initial value set for the counter signal after power-up, which is guaranteed
by XST to be set after the FPGA's GSR signal is de-asserted. by XST to be set after the FPGA's GSR signal is de-asserted.
By default, the reset time is set to 96~$ms$. By default, the reset time is set to 100~$ms$.
%============================================================================== %==============================================================================
% SEC: RTM detection % SEC: RTM detection
...@@ -411,7 +412,7 @@ the blocking output transformers. ...@@ -411,7 +412,7 @@ the blocking output transformers.
Six \textit{ctb\_pulse\_gen} blocks (one per channel) are used for generating blocking and TTL Six \textit{ctb\_pulse\_gen} blocks (one per channel) are used for generating blocking and TTL
pulses at the outputs, based on trigger inputs arriving on the channels. The \textit{ctb\_pulse\_gen} blocks pulses at the outputs, based on trigger inputs arriving on the channels. The \textit{ctb\_pulse\_gen} blocks
are configured for 1.2~${\mu}s$ pulses (\textit{g\_pwidth = 150}, considering the 8~$ns$ clock input). are configured for 1.2~${\mu}$s pulses (\textit{g\_pwidth~=~24}, considering the 50~ns clock input).
%------------------------------------------------------------------------------ %------------------------------------------------------------------------------
% SUBSEC: Implem % SUBSEC: Implem
...@@ -433,7 +434,7 @@ The glitch filter can be used to decrease sensitivity to glitches in noisy envir ...@@ -433,7 +434,7 @@ The glitch filter can be used to decrease sensitivity to glitches in noisy envir
It can be enabled via the \textit{gf\_en\_n\_i} input (connected to SW1.1 on the CONV-TTL-BLO). It can be enabled via the \textit{gf\_en\_n\_i} input (connected to SW1.1 on the CONV-TTL-BLO).
The length of the filter can be set via the \textit{g\_gf\_len} generic. The length of the filter can be set via the \textit{g\_gf\_len} generic.
Enabling the glitch filter will lead to the trigger being sampled using \textit{clk125} Enabling the glitch filter will lead to the trigger being sampled using \textit{clk20\_vcxo\_i}
and introduces leading-edge jitter on the \textit{pulse\_o} output. To avoid this and introduces leading-edge jitter on the \textit{pulse\_o} output. To avoid this
leading-edge pulse jitter, the glitch filter can be left disabled. leading-edge pulse jitter, the glitch filter can be left disabled.
...@@ -444,7 +445,7 @@ The behavior of the outputs are different, depending on the state of the glitch ...@@ -444,7 +445,7 @@ The behavior of the outputs are different, depending on the state of the glitch
With the glitch filter disabled, the input pulse enables the With the glitch filter disabled, the input pulse enables the
input flip-flop, which starts pulse generation. The pulse signal is then synchronized input flip-flop, which starts pulse generation. The pulse signal is then synchronized
in the \textit{clk125} domain and input to the synchronous FSM, which extends the in the \textit{clk20\_vcxo\_i} domain and input to the synchronous FSM, which extends the
pulse to \textit{g\_pwidth}. The rising edge on \textit{SGF0} triggers the counter, pulse to \textit{g\_pwidth}. The rising edge on \textit{SGF0} triggers the counter,
and when the counter reaches the value corresponding to the selected pulse width, and when the counter reaches the value corresponding to the selected pulse width,
it sets the \textit{OGF0} output, which will reset the input flip-flop, thus ending the pulse. it sets the \textit{OGF0} output, which will reset the input flip-flop, thus ending the pulse.
...@@ -481,14 +482,14 @@ Most of this external logic is on the TTL pulse side, where both TTL and TTL-BAR ...@@ -481,14 +482,14 @@ Most of this external logic is on the TTL pulse side, where both TTL and TTL-BAR
pulses may arrive. As described in Section 4.3 of \cite{ctb-ug}, if a wire is not plugged in pulses may arrive. As described in Section 4.3 of \cite{ctb-ug}, if a wire is not plugged in
when TTL-BAR pulses are input, a continuous logic high level on the line would inhibit when TTL-BAR pulses are input, a continuous logic high level on the line would inhibit
pulses arriving on the blocking side from triggering a pulse generation. This is why pulses arriving on the blocking side from triggering a pulse generation. This is why
the \textit{no sig. detect} block has been implemented. the \textit{no signal detect} block has been implemented.
The block's implementation is shown in Figure~\ref{fig:no-sig-detect}. It is implemented as The block's implementation is shown in Figure~\ref{fig:no-sig-detect}. It is implemented as
a counter which keeps the \textit{en\_o} signal high as long as it does not reach its maximum value. a counter which keeps the \textit{en\_o} signal high as long as it does not reach its maximum value.
The counter counts up when the \textit{cnt} input is high. By setting the maximum value The counter counts up when the \textit{cnt} input is high. By setting the maximum value
of the counter to 12499, it disables the line to the multiplexer if this stays high of the counter to 1999, it disables the line to the multiplexer if this stays high
for 100~${\mu}s$, thus allowing for blocking pulses at the input of the OR gate. The line for 100~${\mu}s$, thus allowing for blocking pulses at the input of the OR gate. The line
is re-enabled as soon as it goes back low, i.e., when a wire has been plugged in to the is re-enabled as soon as it goes back low, i.e., when a wire has been plugged into the
channel. channel.
\begin{figure}[h] \begin{figure}[h]
......
top/Release/conv_ttl_blo.ucf
View file @ 81fb2371
...@@ -61,9 +61,9 @@ ...@@ -61,9 +61,9 @@
NET "mr_n_o" LOC = T22; NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33; NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16; NET "clk20_vcxo_i" LOC = E16;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i; NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %; TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12; NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11; NET "fpga_clk_n_i" LOC = G11;
...@@ -311,54 +311,53 @@ NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33"; ...@@ -311,54 +311,53 @@ NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20; NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
###============================================================================= ##=============================================================================
###-- WHITE RABBIT ##-- WHITE RABBIT
###============================================================================= ##=============================================================================
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- Thermo for UID ##-- Thermo for UID
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
#NET "thermometer_b" LOC = B1; NET "thermometer_b" LOC = B1;
#NET "thermometer_b" IOSTANDARD = LVCMOS33; NET "thermometer_b" IOSTANDARD = LVCMOS33;
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- DAC control ##-- DAC control
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
#NET "fpga_plldac1_din_o" LOC = AB14; NET "fpga_plldac1_din_o" LOC = AB14;
#NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sclk_o" LOC = AA14; NET "fpga_plldac1_sclk_o" LOC = AA14;
#NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sync_n_o" LOC = AB15; NET "fpga_plldac1_sync_n_o" LOC = AB15;
#NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
#
#NET "fpga_plldac2_din_o" LOC = W14; NET "fpga_plldac2_din_o" LOC = W14;
#NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sclk_o" LOC = Y14; NET "fpga_plldac2_sclk_o" LOC = Y14;
#NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sync_n_o" LOC = W13; NET "fpga_plldac2_sync_n_o" LOC = W13;
#NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- SFP connection ##-- SFP connection
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
##NET "fpga_sfp_los_i" LOC = G3; NET "fpga_sfp_los_i" LOC = G3;
## NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_mod_def0_i" LOC = K8; NET "fpga_sfp_mod_def0_i" LOC = K8;
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4; NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_sfp_mod_def1_b" LOC = G4; NET "fpga_sfp_mod_def1_b" LOC = G4;
#NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33; NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
# NET "fpga_sfp_mod_def2_b" LOC = F3;
#NET "fpga_sfp_mod_def2_b" LOC = F3; NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
#NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33; NET "fpga_sfp_tx_disable_o" LOC = E4;
##NET "fpga_sfp_tx_disable_o" LOC = E4; NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_tx_fault_i" LOC = D2;
##NET "fpga_sfp_tx_fault_i" LOC = D2; NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- FPGA MGT lines ##-- FPGA MGT lines
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10; #NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10; #NET "fpga_mgt_clk0_n_i" LOC = B10;
# #
...@@ -368,9 +367,9 @@ NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33"; ...@@ -368,9 +367,9 @@ NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
#NET "mgt_sfp_tx0_p_o" LOC = B6; #NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6; #NET "mgt_sfp_tx0_n_o" LOC = A6;
###============================================================================= ##=============================================================================
###-- ADDITIONAL PINS ##-- ADDITIONAL PINS
###============================================================================= ##=============================================================================
NET "fpga_oe_o" LOC = R3; NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33; NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4; NET "fpga_oe_o" DRIVE = 4;
......
top/Release/conv_ttl_blo.vhd
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top/pulsetest/pulsetest.ucf
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...@@ -61,9 +61,9 @@ ...@@ -61,9 +61,9 @@
NET "mr_n_o" LOC = T22; NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33; NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16; NET "clk20_vcxo_i" LOC = E16;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i; NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %; TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12; NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11; NET "fpga_clk_n_i" LOC = G11;
...@@ -309,50 +309,50 @@ NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33"; ...@@ -309,50 +309,50 @@ NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20; NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
###============================================================================= ##=============================================================================
###-- WHITE RABBIT ##-- WHITE RABBIT
###============================================================================= ##=============================================================================
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- Thermo for UID ##-- Thermo for UID
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
#NET "thermometer_b" LOC = B1; NET "thermometer_b" LOC = B1;
#NET "thermometer_b" IOSTANDARD = LVCMOS33; NET "thermometer_b" IOSTANDARD = LVCMOS33;
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- DAC control ##-- DAC control
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
#NET "fpga_plldac1_din_o" LOC = AB14; NET "fpga_plldac1_din_o" LOC = AB14;
#NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sclk_o" LOC = AA14; NET "fpga_plldac1_sclk_o" LOC = AA14;
#NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sync_n_o" LOC = AB15; NET "fpga_plldac1_sync_n_o" LOC = AB15;
#NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
#
#NET "fpga_plldac2_din_o" LOC = W14; NET "fpga_plldac2_din_o" LOC = W14;
#NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sclk_o" LOC = Y14; NET "fpga_plldac2_sclk_o" LOC = Y14;
#NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sync_n_o" LOC = W13; NET "fpga_plldac2_sync_n_o" LOC = W13;
#NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33; NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
###-- SFP connection ##-- SFP connection
###----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
##NET "fpga_sfp_los_i" LOC = G3; NET "fpga_sfp_los_i" LOC = G3;
## NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_mod_def0_i" LOC = K8; NET "fpga_sfp_mod_def0_i" LOC = K8;
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4; NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_sfp_mod_def1_b" LOC = G4; NET "fpga_sfp_mod_def1_b" LOC = G4;
#NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33; NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
#
#NET "fpga_sfp_mod_def2_b" LOC = F3; NET "fpga_sfp_mod_def2_b" LOC = F3;
#NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33; NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
##NET "fpga_sfp_tx_disable_o" LOC = E4; NET "fpga_sfp_tx_disable_o" LOC = E4;
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_tx_fault_i" LOC = D2; NET "fpga_sfp_tx_fault_i" LOC = D2;
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###----------------------------------------------------------------------------- ###-----------------------------------------------------------------------------
###-- FPGA MGT lines ###-- FPGA MGT lines
......
top/pulsetest/pulsetest.vhd
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top/regtest/regtest.ucf
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top/regtest/regtest.vhd
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...@@ -51,8 +51,11 @@ entity regtest is ...@@ -51,8 +51,11 @@ entity regtest is
); );
port port
( (
-- Clock lines -- Clocks
fpga_clk_p_i : in std_logic; --Using the 125MHz clock -- 20 MHz from VCXO
clk20_vcxo_i : in std_logic;
-- 125 MHz from clock generator
fpga_clk_p_i : in std_logic;
fpga_clk_n_i : in std_logic; fpga_clk_n_i : in std_logic;
-- LEDs -- LEDs
...@@ -66,7 +69,28 @@ entity regtest is ...@@ -66,7 +69,28 @@ entity regtest is
led_wr_link_syserror_o : out std_logic; led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic; led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic; led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave -- Lines for the i2c_slave
scl_i : in std_logic; scl_i : in std_logic;
scl_o : out std_logic; scl_o : out std_logic;
...@@ -77,8 +101,40 @@ entity regtest is ...@@ -77,8 +101,40 @@ entity regtest is
fpga_ga_i : in std_logic_vector(4 downto 0); fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic; fpga_gap_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay -- Flash memory lines
mr_n_o : out std_logic fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- Blocking power supply reset line
mr_n_o : out std_logic;
-- Thermometer line
thermometer_b : inout std_logic;
-- PLL DACs
-- DAC1: 20 MHz VCXO control
fpga_plldac1_din_o : out std_logic;
fpga_plldac1_sclk_o : out std_logic;
fpga_plldac1_sync_n_o : out std_logic;
-- DAC2: 125 MHz clock generator control
fpga_plldac2_din_o : out std_logic;
fpga_plldac2_sclk_o : out std_logic;
fpga_plldac2_sync_n_o : out std_logic;
-- SFP lines
fpga_sfp_los_i : in std_logic;
fpga_sfp_mod_def0_i : in std_logic;
fpga_sfp_rate_select_o : out std_logic;
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
fpga_sfp_tx_disable_o : out std_logic;
fpga_sfp_tx_fault_i : in std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
); );
end regtest; end regtest;
...@@ -178,9 +234,6 @@ architecture behav of regtest is ...@@ -178,9 +234,6 @@ architecture behav of regtest is
--============================================================================ --============================================================================
-- Signal declarations -- Signal declarations
--============================================================================ --============================================================================
-- Clock signals
signal clk125 : std_logic;
-- Reset signals -- Reset signals
signal rst_n, rst : std_logic; signal rst_n, rst : std_logic;
...@@ -198,8 +251,8 @@ architecture behav of regtest is ...@@ -198,8 +251,8 @@ architecture behav of regtest is
signal bicolor_led_state : std_logic_vector(23 downto 0); signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals -- I2C bridge signals
signal vbcp_done : std_logic; signal vbcp_tip : std_logic;
signal vbcp_err : std_logic; signal vbcp_err : std_logic;
signal i2c_err_led : std_logic; signal i2c_err_led : std_logic;
signal i2c_up : std_logic; signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0); signal i2c_addr : std_logic_vector(6 downto 0);
...@@ -210,22 +263,6 @@ architecture behav of regtest is ...@@ -210,22 +263,6 @@ architecture behav of regtest is
begin begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf : IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => fpga_clk_p_i,
IB => fpga_clk_n_i,
O => clk125
);
--============================================================================ --============================================================================
-- Internal and external reset generation -- Internal and external reset generation
--============================================================================ --============================================================================
...@@ -238,7 +275,7 @@ begin ...@@ -238,7 +275,7 @@ begin
) )
port map port map
( (
clk_i => clk125, clk_i => clk20_vcxo_i,
rst_i => '0', rst_i => '0',
rst_n_o => rst_n rst_n_o => rst_n
); );
...@@ -257,7 +294,7 @@ begin ...@@ -257,7 +294,7 @@ begin
port map port map
( (
-- Clock, reset -- Clock, reset
clk_i => clk125, clk_i => clk20_vcxo_i,
rst_n_i => rst_n, rst_n_i => rst_n,
-- I2C lines -- I2C lines
...@@ -270,7 +307,7 @@ begin ...@@ -270,7 +307,7 @@ begin
-- I2C address and status -- I2C address and status
i2c_addr_i => i2c_addr, i2c_addr_i => i2c_addr,
tip_o => vbcp_done, tip_o => vbcp_tip,
err_o => vbcp_err, err_o => vbcp_err,
-- Wishbone master signals -- Wishbone master signals
...@@ -286,11 +323,13 @@ begin ...@@ -286,11 +323,13 @@ begin
wbm_err_i => xbar_slave_out(0).err wbm_err_i => xbar_slave_out(0).err
); );
-- Process to blink the LED for a finite amount of time when the vbcp_done -- Process to blink the LED when an I2C transfer is in progress
-- signal is set. -- blinks four times per transfer
p_i2c_blink : process(clk125) -- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk20_vcxo_i)
begin begin
if rising_edge(clk125) then if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0'); led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0'); led_i2c_cnt <= (others => '0');
...@@ -301,13 +340,13 @@ begin ...@@ -301,13 +340,13 @@ begin
when '0' => when '0' =>
led_i2c <= '0'; led_i2c <= '0';
if (vbcp_done = '1') then if (vbcp_tip = '1') then
blink_state <= '1'; blink_state <= '1';
end if; end if;
when '1' => when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1; led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 2499999) then if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0'); led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1; led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c; led_i2c <= not led_i2c;
...@@ -328,9 +367,9 @@ begin ...@@ -328,9 +367,9 @@ begin
-- Process to set the I2C error LED signal for display on the front panel -- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an -- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module. -- error is detected from the bridge module.
p_i2c_err_led : process (clk125) is p_i2c_err_led : process (clk20_vcxo_i) is
begin begin
if rising_edge(clk125) then if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then if (rst_n = '0') then
i2c_err_led <= '0'; i2c_err_led <= '0';
elsif (vbcp_err = '1') then elsif (vbcp_err = '1') then
...@@ -356,7 +395,7 @@ begin ...@@ -356,7 +395,7 @@ begin
) )
port map port map
( (
clk_sys_i => clk125, clk_sys_i => clk20_vcxo_i,
rst_n_i => rst_n, rst_n_i => rst_n,
slave_i => xbar_slave_in, slave_i => xbar_slave_in,
slave_o => xbar_slave_out, slave_o => xbar_slave_out,
...@@ -374,7 +413,7 @@ begin ...@@ -374,7 +413,7 @@ begin
) )
port map ( port map (
rst_n_i => rst_n, rst_n_i => rst_n,
clk_i => clk125, clk_i => clk20_vcxo_i,
bwe_i => (others => '0'), bwe_i => (others => '0'),
we_i => ram_we, we_i => ram_we,
a_i => xbar_master_out(c_slv_mem).adr(11 downto 0), a_i => xbar_master_out(c_slv_mem).adr(11 downto 0),
...@@ -388,9 +427,9 @@ begin ...@@ -388,9 +427,9 @@ begin
xbar_master_in(c_slv_mem).ack <= ram_ack; xbar_master_in(c_slv_mem).ack <= ram_ack;
xbar_master_in(c_slv_mem).err <= '0'; xbar_master_in(c_slv_mem).err <= '0';
p_ram_ack : process (clk125) is p_ram_ack : process (clk20_vcxo_i) is
begin begin
if rising_edge(clk125) then if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then if (rst_n = '0') then
ram_ack <= '0'; ram_ack <= '0';
else else
...@@ -453,12 +492,12 @@ begin ...@@ -453,12 +492,12 @@ begin
( (
g_NB_COLUMN => 6, g_NB_COLUMN => 6,
g_NB_LINE => 2, g_NB_LINE => 2,
g_clk_freq => 125000000, g_clk_freq => 20000000,
g_refresh_rate => 250 g_refresh_rate => 250
) )
port map port map
( (
clk_i => clk125, clk_i => clk20_vcxo_i,
rst_n_i => rst_n, rst_n_i => rst_n,
led_intensity_i => "1111111", led_intensity_i => "1111111",
led_state_i => bicolor_led_state, led_state_i => bicolor_led_state,
...@@ -474,4 +513,41 @@ begin ...@@ -474,4 +513,41 @@ begin
line_oen_o(1) => led_ctrl1_oen_o line_oen_o(1) => led_ctrl1_oen_o
); );
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- Theremometer output to high-impedance
thermometer_b <= 'Z';
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o <= '1';
fpga_plldac1_din_o <= '0';
fpga_plldac1_sclk_o <= '0';
fpga_plldac2_sync_n_o <= '1';
fpga_plldac2_din_o <= '0';
fpga_plldac2_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
fpga_sfp_rate_select_o <= 'Z';
fpga_sfp_mod_def1_b <= 'Z';
fpga_sfp_mod_def2_b <= 'Z';
fpga_sfp_tx_disable_o <= 'Z';
-- Pulse outputs and pulse LEDs
fpga_oe_o <= '0';
fpga_blo_oe_o <= '0';
fpga_trig_ttl_oe_o <= '0';
fpga_inv_oe_o <= '0';
pulse_front_led_n_o <= (others => '0');
pulse_rear_led_n_o <= (others => '0');
fpga_out_ttl_o <= (others => '0');
fpga_trig_blo_o <= (others => '0');
inv_out_o <= (others => '0');
-- Flash outputs
fpga_prom_cclk_o <= '0';
fpga_prom_cso_b_n_o <= '1';
fpga_prom_mosi_o <= '0';
end behav; end behav;
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