hdl: Added simulation files and projects

- conv_pulse_gen - conv_man_trig Signed-off-by: Theodor Stana <t.stana@cern.ch>

hdl: Added simulation files and projects
- conv_pulse_gen - conv_man_trig Signed-off-by: Theodor Stana <t.stana@cern.ch>
80e35812 · Theodor-Adrian Stana · 0c3e9fc3 · 80e35812 · 80e35812 · 80e35812
Commit 80e35812 authored Jan 30, 2014 by Theodor-Adrian Stana
6 changed files
--- a/sim/conv_man_trig/run.do
+++ b/sim/conv_man_trig/run.do
+vlib work
+
+vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
+vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
+
+vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
+vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
+vcom -explicit -93 "../../modules/Release/conv_pulse_gen.vhd"
+
+vcom -explicit -93 "../../modules/Release/conv_man_trig.vhd"
+
+vcom -explicit -93 "testbench.vhd"
+
+vsim -t 1ps -voptargs="+acc" -lib work work.testbench
+
+radix -hexadecimal
+# add wave *
+do wave.do
+
+run 300 us
+wave zoomfull
--- a/sim/conv_man_trig/testbench.vhd
+++ b/sim/conv_man_trig/testbench.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Testbench for the manual trigger module
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2014-01-30
+--
+-- version: 1.0
+--
+-- description:
+--
+-- dependencies:
+--
+-- references:
+--
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2014-01-30   Theodor Stana     File created
+--==============================================================================
+-- TODO: -
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.genram_pkg.all;
+
+entity testbench is
+end entity testbench;
+
+
+architecture behav of testbench is
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  constant c_clk_per : time := 50 ns;
+  constant c_reset_width : time := 31 ns;
+  constant c_gf_len  : positive := 1;
+
+  --============================================================================
+  -- Functions and procedures
+  --============================================================================
+  procedure f_mantrig
+  (
+    constant chan   : in  integer;
+    signal   mpt    : out std_logic_vector(7 downto 0);
+    signal   mpt_wr : out std_logic
+  ) is
+  begin
+    wait for 1 us;
+    mpt    <= x"de";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= x"ad";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= x"be";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= x"ef";
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt    <= std_logic_vector(to_unsigned(chan, 8));
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+    wait for 1 us;
+    mpt_wr <= '1';
+    wait for c_clk_per;
+    mpt_wr <= '0';
+  end procedure;
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+  -- DUT
+  component conv_man_trig is
+    generic
+    (
+      -- Number of conversion channels
+      g_nr_chan : positive := 6;
+
+      -- Glitch filter length, to generate a long enough pulse
+      g_gf_len  : positive := 1
+    );
+    port
+    (
+      -- Clock, active-low inputs
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+
+      -- Control inputs from conv_regs
+      reg_ld_i : in  std_logic;
+      reg_i    : in  std_logic_vector(7 downto 0);
+
+      -- One-clock pulse output
+      trig_o   : out std_logic_vector(g_nr_chan downto 1)
+    );
+  end component conv_man_trig;
+
+
+  -- Pulse generator driven by DUT
+  component conv_pulse_gen is
+    generic
+    (
+      -- Pulse width, in number of clk_i cycles
+      -- Default pulse width (20 MHz clock): 1.2 us
+      -- Minimum allowable pulse width (20 MHz clock): 1 us
+      -- Maximum allowable pulse width (20 MHz clock): 2 us
+      g_pwidth : natural range 20 to 40 := 24;
+
+      -- Glitch filter length:
+      -- g_gf_len=1 => trigger width should be > 1 clk_i cycle
+      -- g_gf_len=2 => trigger width should be > 2 clk_i cycles
+      -- etc.
+      g_gf_len : natural := 1
+    );
+    port
+    (
+      -- Clock and active-low reset inputs
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+
+      -- Glitch filter enable input
+      -- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
+      -- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
+      gf_en_n_i : in  std_logic;
+
+      -- Enable input, pulse generation is enabled when '1'
+      en_i      : in  std_logic;
+
+      -- Trigger input, has to be '1' to assure pulse output with delay no greater
+      -- than internal gate delays.
+      trig_a_i  : in  std_logic;
+
+      -- Pulse output, active-high
+      -- latency:
+      --    glitch filter disabled : none
+      --    glitch filter enabled  : g_gf_len+6 clk_i cycles
+      pulse_o   : out std_logic
+    );
+  end component conv_pulse_gen;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal clk20     : std_logic := '0';
+  signal rst_n     : std_logic;
+  signal mpt_wr    : std_logic;
+  signal mpt_wr_d0 : std_logic;
+  signal mpt_ld    : std_logic;
+  signal mpt       : std_logic_vector(7 downto 0);
+  signal trig_man  : std_logic_vector(6 downto 1);
+  signal pulse     : std_logic_vector(6 downto 1);
+  signal gf_n        : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- Generate clock and reset signals
+  --============================================================================
+  p_clk: process
+  begin
+    clk20 <= not clk20;
+    wait for c_clk_per/2;
+  end process p_clk;
+
+  p_rst_n: process
+  begin
+    rst_n <= '0';
+    wait for c_reset_width;
+    rst_n <= '1';
+    wait;
+  end process p_rst_n;
+
+  --============================================================================
+  -- Instantiate DUT and conv_pulse_gen blocks it drives
+  --============================================================================
+  -- First, the DUT
+  cmp_dut : conv_man_trig
+    generic map
+    (
+      g_nr_chan => 6,
+      g_gf_len  => c_gf_len
+    )
+    port map
+    (
+      clk_i    => clk20,
+      rst_n_i  => rst_n,
+
+      reg_ld_i => mpt_ld,
+      reg_i    => mpt,
+
+      trig_o   => trig_man
+    );
+
+  -- Then, the pulse generators with a generate statement
+  gen_pulse_gens : for i in 1 to 6 generate
+    cmp_pulse_gen : conv_pulse_gen
+      generic map
+      (
+        g_pwidth => 24,
+        g_gf_len => c_gf_len
+      )
+      port map
+      (
+        clk_i     => clk20,
+        rst_n_i   => rst_n,
+        gf_en_n_i => gf_n,
+        en_i      => '1',
+        trig_a_i  => trig_man(i),
+        pulse_o   => pulse(i)
+      );
+  end generate gen_pulse_gens;
+
+  --============================================================================
+  -- Some stimuli for the DUT
+  --============================================================================
+  p_mpt_ld : process (clk20)
+  begin
+    if rising_edge(clk20) then
+      if rst_n = '0' then
+        mpt_ld    <= '0';
+        mpt_wr_d0 <= '0';
+      else
+        mpt_wr_d0 <= mpt_wr;
+        mpt_ld    <= mpt_wr and not mpt_wr_d0;
+      end if;
+    end if;
+  end process;
+
+  p_stim : process
+  begin
+    mpt_wr <= '0';
+    mpt    <= (others => '0');
+    --------------------------
+    -- No glitch filt
+    --------------------------
+    gf_n <= '1';
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    --------------------------
+    -- With glitch filt
+    --------------------------
+    gf_n <= '0';
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    gf_n <= '1';
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    --------------------------
+    -- No glitch filt
+    --------------------------
+    gf_n <= '1';
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(6, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    gf_n <= '0';
+    f_mantrig(5, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(4, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(3, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(2, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    f_mantrig(1, mpt, mpt_wr);
+    wait for 1 us;
+    wait;
+  end process p_stim;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/sim/conv_man_trig/wave.do
+++ b/sim/conv_man_trig/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk20
+add wave -noupdate /testbench/rst_n
+add wave -noupdate /testbench/mpt_ld
+add wave -noupdate /testbench/mpt
+add wave -noupdate /testbench/trig_man
+add wave -noupdate -expand /testbench/pulse
+add wave -noupdate -divider DUT
+add wave -noupdate /testbench/cmp_dut/state
+add wave -noupdate /testbench/cmp_dut/pass
+add wave -noupdate /testbench/cmp_dut/chnr
+add wave -noupdate /testbench/cmp_dut/cnt
+add wave -noupdate /testbench/cmp_dut/trig_o
+add wave -noupdate -divider {glitch filt}
+add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/gf_en_n_i
+add wave -noupdate -divider {pulse gen}
+add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_on
+add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_off
+add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_on
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {218986486 ps} 0} {{Cursor 2} {74966216 ps} 0}
+configure wave -namecolwidth 383
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {315 us}
--- a/sim/conv_pulse_gen/run.do
+++ b/sim/conv_pulse_gen/run.do
+vlib work
+
+vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
+vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
+
+vcom -explicit -93 "../../modules/pulsetest/pulse_gen_gp.vhd"
+vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
+vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
+
+vcom -explicit -93 "../../modules/Release/conv_pulse_gen.vhd"
+vcom -explicit -93 "../../modules/Release/conv_man_trig.vhd"
+
+vcom -explicit -93 "testbench.vhd"
+
+vsim -t 1ps -voptargs="+acc" -lib work work.testbench
+
+radix -hexadecimal
+# add wave *
+do wave.do
+
+run 100 us
+wave zoomfull
--- a/sim/conv_pulse_gen/testbench.vhd
+++ b/sim/conv_pulse_gen/testbench.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Testbench for old repeater design
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity testbench is
+end entity testbench;
+
+
+architecture behav of testbench is
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  constant c_clk_per : time := 50 ns;
+  constant c_reset_width : time := 31 ns;
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+  component conv_pulse_gen is
+    generic
+    (
+      -- Pulse width, in number of clk_i cycles
+      -- Default pulse width (20 MHz clock): 1.2 us
+      -- Minimum allowable pulse width (20 MHz clock): 1 us
+      -- Maximum allowable pulse width (20 MHz clock): 2 us
+      g_pwidth : natural range 20 to 40 := 24;
+
+      -- Glitch filter length:
+      -- g_gf_len=1 => trigger width should be > 1 clk_i cycle
+      -- g_gf_len=2 => trigger width should be > 2 clk_i cycles
+      -- etc.
+      g_gf_len : natural := 1
+    );
+    port
+    (
+      -- Clock and active-low reset inputs
+      clk_i     : in  std_logic;
+      rst_n_i   : in  std_logic;
+
+      -- Glitch filter enable input
+      -- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
+      -- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
+      gf_en_n_i : in  std_logic;
+
+      -- Enable input, pulse generation is enabled when '1'
+      en_i      : in  std_logic;
+
+      -- Trigger input, has to be '1' to assure pulse output with delay no greater
+      -- than internal gate delays.
+      trig_a_i  : in  std_logic;
+
+      -- Pulse output, active-high
+      -- latency:
+      --    glitch filter disabled : none
+      --    glitch filter enabled  : g_gf_len+6 clk_i cycles
+      pulse_o   : out std_logic
+    );
+  end component conv_pulse_gen;
+
+  component pulse_gen_gp is
+    port
+    (
+      -- Input clock and active-low reset
+      clk_i    : in  std_logic;
+      rst_n_i  : in  std_logic;
+
+      -- Active high enable signal
+      en_i     : in  std_logic;
+
+      -- Delay, pulse width and frequency inputs, in number of clk_i cycles
+      delay_i  : in  std_logic_vector(31 downto 0);
+      pwidth_i : in  std_logic_vector(31 downto 0);
+      freq_i   : in  std_logic_vector(31 downto 0);
+
+      -- Output pulse signal
+      pulse_o  : out std_logic
+    );
+  end component pulse_gen_gp;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
+  signal actual_trig  : std_logic := '0';
+  signal actual_pulse : std_logic := '0';
+  signal gf_en        : std_logic;
+  signal gf_en_n      : std_logic;
+  signal pgen_en      : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  -- DUT INSTANTIATION
+  DUT: conv_pulse_gen
+    generic map
+    (
+      g_pwidth => 24,
+      g_gf_len => 1
+    )
+    port map
+    (
+      clk_i     => clk,
+      rst_n_i   => rst_n,
+      gf_en_n_i => gf_en_n,
+      en_i      => '1',
+      trig_a_i  => actual_trig,
+      pulse_o   => pulse
+    );
+
+  -- CLOCK GENERATION
+  p_clk: process
+  begin
+    clk <= not clk;
+    wait for c_clk_per/2;
+  end process p_clk;
+
+  -- SECOND CLOCK GENERATION
+  p_clk2: process
+  begin
+    clk2 <= not clk2;
+    wait for 2 ns;
+  end process p_clk2;
+
+  -- RESET GENERATION
+  p_rst_n: process
+  begin
+    rst_n <= '0';
+    wait for c_reset_width;
+    rst_n <= '1';
+    wait;
+  end process p_rst_n;
+
+  -- PULSE GENERATOR FOR TRIGGER
+  cmp_pulse_gen : pulse_gen_gp
+  port map
+  (
+    clk_i    => clk2,
+    rst_n_i  => rst_n,
+    en_i     => pgen_en,
+    delay_i  => (others => '0'),
+    pwidth_i => x"00000019",
+    freq_i   => x"000006dd",
+    pulse_o  => trig
+  );
+
+  actual_trig  <= trig;
+  actual_pulse <= pulse;
+
+  -- PULSE GENERATOR FOR GF_EN
+  cmp_pulse_gen_gp: pulse_gen_gp
+  port map
+  (
+    clk_i    => clk,
+    rst_n_i  => rst_n,
+    en_i     => '1',
+    delay_i  => (others => '0'),
+    pwidth_i => x"00000409",
+    freq_i   => x"00000812",
+    pulse_o  => gf_en
+  );
+
+  pgen_en <= '1';
+  gf_en_n <= '1';
+
+--  p_gf_en : process
+--  begin
+--    gf_en_n <= '1';
+--    pgen_en <= '1';
+--    wait for 50 us;
+--    gf_en_n <= '0';
+--    wait for 24 us;
+--    pgen_en <= '0';
+--    wait for 1 us;
+--    gf_en_n <= '1';
+--    wait for 1 us;
+--    pgen_en <= '1';
+--    wait;
+--  end process;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/sim/conv_pulse_gen/wave.do
+++ b/sim/conv_pulse_gen/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/pulse
+add wave -noupdate /testbench/trig
+add wave -noupdate /testbench/actual_trig
+add wave -noupdate /testbench/actual_pulse
+add wave -noupdate /testbench/gf_en
+add wave -noupdate /testbench/gf_en_n
+add wave -noupdate -divider ctb_pulse_gen
+add wave -noupdate /testbench/DUT/pulse_o
+add wave -noupdate /testbench/DUT/trig_a_i
+add wave -noupdate /testbench/DUT/trig_degl
+add wave -noupdate /testbench/DUT/trig_degl_d0
+add wave -noupdate /testbench/DUT/state
+add wave -noupdate /testbench/DUT/pulse_cnt
+add wave -noupdate /testbench/DUT/pulse_gf_off
+add wave -noupdate /testbench/DUT/pulse_gf_off_d0
+add wave -noupdate /testbench/DUT/pulse_gf_off_d1
+add wave -noupdate /testbench/DUT/pulse_gf_off_d2
+add wave -noupdate -divider GF
+add wave -noupdate /testbench/DUT/pulse_rst
+add wave -noupdate /testbench/DUT/cmp_glitch_filt/dat_o
+add wave -noupdate /testbench/DUT/cmp_glitch_filt/glitch_filt
+add wave -noupdate /testbench/DUT/cmp_glitch_filt/dat_synced
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {32036000 ps} 0} {{Cursor 2} {32350000 ps} 0}
+configure wave -namecolwidth 253
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {30395372 ps} {33676628 ps}