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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
737a6b17
Commit
737a6b17
authored
Sep 30, 2014
by
Theodor-Adrian Stana
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doc: Added license in hdlg and fixed some figures
parent
a84c96f8
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5 changed files
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83 additions
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66 deletions
+83
-66
conv-regs.tex
doc/hdlg/conv-regs.tex
+1
-1
block-diagram.svg
doc/hdlg/fig/block-diagram.svg
+47
-52
no-sig-detect.svg
doc/hdlg/fig/no-sig-detect.svg
+17
-7
hdlg-conv-ttl-blo.bib
doc/hdlg/hdlg-conv-ttl-blo.bib
+1
-1
hdlg-conv-ttl-blo.tex
doc/hdlg/hdlg-conv-ttl-blo.tex
+17
-5
No files found.
doc/hdlg/conv-regs.tex
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737a6b17
...
...
@@ -1550,7 +1550,7 @@ Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\
FRONTINV
}
[
\emph
{
read-only
}
]: Front panel INV-TTL input state
\\
Line state at board input
\\
Bit 0 -- channel
1
\\
Bit 1 -- channel 2
\\
etc.
Line state at board input
\\
Bit 0 -- channel
A
\\
Bit 1 -- channel B
\\
Bit 2 -- channel C
\\
Bit 3 -- channel D
\end{small}
\item
\begin{small}
{
\bf
...
...
doc/hdlg/fig/block-diagram.svg
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737a6b17
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...
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doc/hdlg/fig/no-sig-detect.svg
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737a6b17
...
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doc/hdlg/hdlg-conv-ttl-blo.bib
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737a6b17
...
...
@@ -93,7 +93,7 @@
}
@misc{conv-ttl-blo-sch,
title = {{CONV-TTL-BLO on CERN EDMS}}
}
,
title = {{CONV-TTL-BLO on CERN EDMS}},
howpublished = {\url{https://edms.cern.ch/nav/EDA-02446}}
}
...
...
doc/hdlg/hdlg-conv-ttl-blo.tex
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737a6b17
...
...
@@ -49,8 +49,20 @@
% Revision history
%------------------------------------------------------------------------------
\pagebreak
\addcontentsline
{
toc
}{
section
}{
Revision history
}
\thispagestyle
{
empty
}
\addcontentsline
{
toc
}{
section
}{
Licensing information
}
\section*
{
Licensing information
}
\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see
\\
\url
{
http://creativecommons.org/licenses/by-sa/4.0/
}
\section*
{
Revision history
}
\addcontentsline
{
toc
}{
section
}{
Revision history
}
\centerline
{
...
...
@@ -158,10 +170,10 @@ to the on-board Schmitt-trigger buffer), the \textit{no signal detect} block
to allow propagation of blocking pulses arriving on the rear panel while the channel
has no cable plugged in while in TTL-BAR mode.
When in TTL-BAR mode, the FRONT
INV
bits of the lines status register
When in TTL-BAR mode, the FRONT
FS
bits of the lines status register
(LSR -- see Appendix~
\ref
{
app:conv-regs-lsr
}
) contain the state of the no signal detect
block for each channel and can be used to check if no cable is plugged into the channel.
When in TTL mode, the FRONT
INV
bits are unused.
When in TTL mode, the FRONT
FS
bits are unused.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=\textwidth]
{
fig/ttl-inp
}}
...
...
@@ -214,10 +226,10 @@ active-high. As seen in Figure~\ref{fig:line-inp}, only the TTL and INV-TTL line
need adaptation in the case of the CONV-TTL-BLO, since the blocking inputs are
already adapted on-board for active-high logic.
When in TTL-BAR mode, the FRONT
INV
bits of the lines status register
When in TTL-BAR mode, the FRONT
FS
bits of the lines status register
(LSR -- see Appendix~
\ref
{
app:conv-regs-lsr
}
) contain the state of the no signal detect
block for each channel and can be used to check if no cable is plugged into the channel.
When in TTL mode, the FRONT
INV
bits are unused.
When in TTL mode, the FRONT
FS
bits are unused.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=\textwidth]
{
fig/line-inp
}}
...
...
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