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C
Conv TTL Blocking - Gateware
Commit 72ed130e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add ctblo_pulse_gen from master branch 

This fixes:
1. the max. pulse repetition rate (now 1/200)
2. adds the first pulse inhibit mechanism when the board is in TTL-BAR mode
parent 5592ad8a
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Showing with 301 additions and 385 deletions
modules/Manifest.py
View file @ 72ed130e
......@@ -7,7 +7,6 @@ modules = {
}
files = [
"ctb_pulse_gen.vhd",
"reset_gen.vhd",
"rtm_detector.vhd"
]
modules/Release/Manifest.py
View file @ 72ed130e
files = [
"conv_regs.vhd"
"conv_regs.vhd",
"ctblo_pulse_gen.vhd"
];
modules/ctb_pulse_gen.vhd → modules/Release/ctblo_pulse_gen.vhd
View file @ 72ed130e
......@@ -11,14 +11,11 @@
--
-- description:
-- This module generates a constant-width pulse. The width is set using the
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i
-- period of 8ns, the output pulse width is by default 8*16=128ns.
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i period of
-- 50 ns, the output pulse width is by default 50*24=1.2 us.
--
-- The module contains a variable length filter, with the length adjustable
-- in clock cycle units via the g_gf_len generic. The glitch filter can be used
-- to avoid a signal being generated as a result of a short glitch on the input.
--
-- Enabling the glitch filter will result in jitter on the leading edge of the
-- The module is designed to work with an external glitch filter. Enabling
-- this glitch filter will result in jitter on the leading edge of the
-- output pulse signal. This jitter can be avoided by bypassing the glitch
-- filter; this is done via the gf_en_n_i input.
--
......@@ -26,8 +23,8 @@
-- is extended or cut to g_pwidth, if it is shorter or respectively longer than
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- isolation transformers on the CONV-TTL-BLO boards. The isolation phase
-- limits the input pulse at a 1/5 duty cycle.
-- blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
-- the input pulse to 1/500 duty cycle.
--
-- dependencies:
-- none
......@@ -46,8 +43,12 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 01-03-2013 Theodor Stana File created
-- 02-08-2013 Theodor Stana Implemented rejection phase
-- 01-03-2013 Theodor Stana File created.
-- 02-08-2013 Theodor Stana Implemented rejection phase.
-- 17-02-2014 Theodor Stana Moved the glitch filter to outside the
-- module.
-- 04-03-2014 Theodor Stana Added first pulse inhibit on glitch-filtered
-- side.
--==============================================================================
-- TODO: -
--==============================================================================
......@@ -56,9 +57,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity ctb_pulse_gen is
entity ctblo_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
......@@ -67,11 +66,8 @@ entity ctb_pulse_gen is
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Glitch filter length:
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_gf_len : natural := 1
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
......@@ -91,16 +87,20 @@ entity ctb_pulse_gen is
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_gf_len+5 clk_i cycles
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end entity ctb_pulse_gen;
end entity ctblo_pulse_gen;
architecture behav of ctb_pulse_gen is
architecture behav of ctblo_pulse_gen is
--============================================================================
-- Type declarations
......@@ -116,12 +116,27 @@ architecture behav of ctb_pulse_gen is
--============================================================================
-- Constant declarations
--============================================================================
-- Max value of pulse counter for pulse width and pulse rejection width; see
-- below for explanation for their values
-- Max value of pulse counter for pulse width and pulse rejection width.
-- glitch filter OFF:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- * g_pwidth-4: three-cycle delay through synchronizer
-- * g_pwidth-5: reset signal applied in REJ_GF_OFF state
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-- glitch filter ON:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := 5*g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 5;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := 5*g_pwidth-1;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
--============================================================================
-- Function and procedure declarations
......@@ -139,21 +154,27 @@ architecture behav of ctb_pulse_gen is
--============================================================================
-- Signal declarations
--============================================================================
-- Deglitched trigger
signal trig_degl : std_logic;
signal trig_degl_d0 : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(6*g_pwidth)-1 downto 0);
-- Pulse-specific signals
signal pulse_gf_off : std_logic;
-- Trigger signals
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal pulse_rst : std_logic;
signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic;
signal trig_gf_on_r_edge_p : std_logic;
-- Pulse output signals
signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic;
-- Inhibit first pulse
signal inh_fp_gf_on : std_logic;
signal inh_fp_gf_on_d0 : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
-- FSM signal
signal state : t_state;
......@@ -173,18 +194,18 @@ begin
-- Pulse generation logic
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off: process(pulse_rst, trig_a_i)
p_pulse_gf_off: process(pulse_gf_off_rst, trig_a_i)
begin
if (pulse_rst = '1') then
if (pulse_gf_off_rst = '1') then
pulse_gf_off <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') then
if (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off <= '1';
end if;
end if;
end process p_pulse_gf_off;
-- and synchronize it in clk_i domain
-- and synchronize the trigger in clk_i domain
p_sync_pulse_gf_off: process (clk_i) is
begin
if rising_edge(clk_i) then
......@@ -192,47 +213,66 @@ begin
pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0';
elsif (en_i = '1') then
pulse_gf_off_r_edge_p <= '0';
elsif (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1;
pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
end if;
end if;
end process p_sync_pulse_gf_off;
--============================================================================
-- Glitch filtration logic
--============================================================================
cmp_glitch_filt : gc_glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => trig_a_i,
dat_o => trig_degl
);
-- Trigger signal with glitch filter ON is input signal
trig_gf_on <= trig_a_i;
-- Rising edge detector for the trigger signal when glitch filter is ON
p_trig_gf_on : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
trig_gf_on_d0 <= '0';
trig_gf_on_r_edge_p <= '0';
else
trig_gf_on_d0 <= trig_gf_on;
trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
end if;
end if;
end process p_trig_gf_on;
--============================================================================
-- Pulse width adjustment logic
--============================================================================
-- Generate the FSM logic
p_pulse_width: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
pulse_rst <= '1';
pulse_gf_off_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
trig_degl_d0 <= '0';
inh_fp_gf_on <= '1';
inh_fp_gf_on_d0 <= '1';
pulse_err_p_o <= '0';
elsif (en_i = '1') then
-- Deglitched trigger delay
trig_degl_d0 <= trig_degl;
-- On the first two cycle after reset, the pulse channel needs to be
-- inhibited when the converter board is in TTL-BAR repetition mode,
-- since in this mode, an unconnected channel is HIGH for the first
-- 100us until the "no signal detect" block triggers, and the HIGH level
-- on the line will get interpreted by the trigger delay (due to its reset
-- state) as a rising edge on the line, thus triggering a pulse.
--
-- This is only needed when the glitch filter is ON, since when it is OFF,
-- as the unconnected channel is HIGH for the first 100us, no rising-edge
-- on the channel exists and the p_pulse_gf_off process above is not
-- triggered.
inh_fp_gf_on_d0 <= inh_fp_gf_on;
if inh_fp_gf_on = '1' then
inh_fp_gf_on <= '0';
end if;
-- State machine
-- State machine logic
case state is
---------------------------------------------------------------------
-- IDLE
......@@ -242,13 +282,14 @@ begin
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
pulse_rst <= '0';
pulse_gf_off_rst <= '0';
pulse_err_p_o <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_d1 = '1') and (pulse_gf_off_d2 = '0') then
if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF;
end if;
else
if (trig_degl = '1') and (trig_degl_d0 = '0') then
if (trig_gf_on_r_edge_p = '1') and (inh_fp_gf_on_d0 = '0') then
state <= GEN_GF_ON;
end if;
end if;
......@@ -256,66 +297,78 @@ begin
---------------------------------------------------------------------
-- GEN_GF_OFF
---------------------------------------------------------------------
-- Increment pulse counter to pulse width value.
--
-- Max value: g_pwidth-5 due to:
-- 1. pulse_cnt starts from 0 => g_pwidth-1
-- 2. three cycle delay in clock sync FFs
-- 3. one cycle delay due to reset in next state
--
-- No clock cycle delay for switching from IDLE to GEN_GF_ON,
-- since pulse is already generated on rising edge of trig_a_i
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_gen_gf_off) then
state <= REJ_GF_OFF;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_OFF
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
-- Cut and reject input pulses, to safeguard the output transformers.
---------------------------------------------------------------------
when REJ_GF_OFF =>
pulse_rst <= '1';
-- Pulse logic and state change
pulse_gf_off_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_off) then
state <= IDLE;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_ON
---------------------------------------------------------------------
-- Increment counter to pulse width value and generate glitch-filtered
-- pulse while incrementing.
--
-- Max value: g_pwidth-1, since pulse_cnt starts from 0
-- Start generating the output pulse with the required width.
---------------------------------------------------------------------
when GEN_GF_ON =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_ON
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
-- Stop generating the output pulse and reject incoming pulses.
---------------------------------------------------------------------
when REJ_GF_ON =>
-- Pulse logic and state change
pulse_gf_on <= '0';
pulse_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
when others =>
state <= IDLE;
......
syn/Golden/Makefile
View file @ 72ed130e
......@@ -22,158 +22,3 @@ clean:
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/Golden/conv_ttl_blo.ucf \
../../top/Golden/conv_ttl_blo.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/ctb_pulse_gen.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
conv_ttl_blo.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/Golden/conv_ttl_blo.xise
View file @ 72ed130e
......@@ -341,13 +341,13 @@
<file xil_pn:name="../../top/Golden/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../top/Golden/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../modules/Release/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../modules/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/Release/ctblo_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../modules/reset_gen.vhd" xil_pn:type="FILE_VHDL">
......@@ -356,16 +356,16 @@
<file xil_pn:name="../../modules/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
......@@ -389,300 +389,312 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../top/Golden/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
</files>
<bindings/>
......
top/Golden/conv_ttl_blo.vhd
View file @ 72ed130e
......@@ -235,7 +235,7 @@ architecture behav of conv_ttl_blo is
-- Pulse generator component
-- (use: output pulse generation, pulse status LEDs)
component ctb_pulse_gen is
component ctblo_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
......@@ -244,11 +244,8 @@ architecture behav of conv_ttl_blo is
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Glitch filter length:
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_gf_len : natural := 1
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
......@@ -268,13 +265,17 @@ architecture behav of conv_ttl_blo is
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_gf_len+5 clk_i cycles
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end component ctb_pulse_gen;
end component ctblo_pulse_gen;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
......@@ -734,7 +735,12 @@ begin
end process p_ttlbar_nosig;
-- Output pulse generators
cmp_ttl_pulse_gen : ctb_pulse_gen
cmp_ttl_pulse_gen : ctblo_pulse_gen
generic map
(
g_pwidth => 24,
g_duty_cycle_div => 200
)
port map
(
clk_i => clk20_vcxo_i,
......
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