Commit 6918e787 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Testbench for burst mode testing updated. The overall gateware testbench also…

Testbench for burst mode testing updated. The overall gateware testbench also updated to show burst mode operation for short pulses
parent ce0a347a
......@@ -47,7 +47,7 @@ use std.textio.all;
--use work.gencores_pkg.all;
--use work.wishbone_pkg.all;
-- use work.conv_common_gw_pkg.all;
use work.conv_common_gw_pkg.all;
entity testbench is
end entity testbench;
......@@ -58,37 +58,12 @@ architecture behav of testbench is
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant random_intervals : boolean := false;
component conv_burst_ctrl is
generic
(
g_pwidth : natural range 1 to 10 := 5;
g_duty_cycle_div : natural := 200;
g_max_burst_len : natural := 1000;
g_burst_timeout : natural := 60000
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
burst_err_p_o : out std_logic
);
end component conv_burst_ctrl;
component conv_dyn_burst_ctrl is
generic
(
g_pwidth : natural range 2 to 40 := 5;
g_temp_decre_step : t_temp_decre_step := (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
g_1_pulse_temp_rise :in unsigned (19 downto 0);
g_max_temp :in unsigned (39 downto 0)
);
......@@ -101,8 +76,6 @@ architecture behav of testbench is
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
pulse_burst_i : in std_logic;
temp_rise_c : out unsigned (39 downto 0);
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
......@@ -123,7 +96,6 @@ architecture behav of testbench is
--signal burst_train_dyn : std_logic;
signal burst_train_regulated : std_logic;
signal burst_train_regulated_dyn : std_logic;
signal temp_rise_counter : unsigned (39 downto 0) ;
signal rand_num : integer := 0;
......@@ -139,40 +111,24 @@ architecture behav of testbench is
-- ===========================================================================
--Instantiate the DUT: Burst controller averaged over 1000 pulses
--============================================================================
cmp_dut_1 : conv_burst_ctrl
generic map
(
g_pwidth => 5,
g_duty_cycle_div => 2,
g_max_burst_len => 3,
g_burst_timeout => 50000
)
port map(
clk_i => clk_20,
rst_n_i => rst,
en_i => en,
pulse_burst_i => burst_train,
pulse_burst_o => burst_train_regulated,
burst_err_p_o => open
);
-- burst_train_dyn <= burst_train;
--============================================================================
-- Instantiate the DUT: Dynamic
--============================================================================
cmp_dut_2 : conv_dyn_burst_ctrl
cmp_dut : conv_dyn_burst_ctrl
generic map
(
g_pwidth => 5, --
g_1_pulse_temp_rise => x"01388",
--g_1_pulse_temp_rise => x"23040", - for 1.2us pulse
--g_1_pulse_temp_rise => x"7A125",
--g_max_temp => x"00000F4240" --10^6
--g_temp_decre_step => (0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13),
g_temp_decre_step => (0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0),
g_1_pulse_temp_rise => x"01388",
--g_1_pulse_temp_rise => x"23040", -- for 1.2us pulse
g_max_temp => x"00000F4240" --10^6
g_max_temp => x"02540BE400" --10^10
--g_max_temp => x"02540BE400" --10^10
)
port map(
clk_i => clk_20,
......@@ -182,7 +138,6 @@ architecture behav of testbench is
pulse_burst_i => burst_train,
pulse_burst_o => burst_train_regulated_dyn,
temp_rise_c => temp_rise_counter,
burst_err_p_o => open
);
......@@ -242,7 +197,7 @@ end process p_ran_gen;
variable interval : time;-- := 1000 ns;
begin
while t_sim1 < 7000000 us loop
while t_sim1 < 50000 us loop
--while true loop
t_sim1 <= NOW - t_start;
if random_intervals then
......@@ -251,7 +206,7 @@ end process p_ran_gen;
interval := 250 ns;
end if;
else
interval := 1600 ns;--changes pulse frequency
interval := 250 ns;--changes pulse frequency
end if;
burst_train <= '0';
wait for interval;
......@@ -260,7 +215,7 @@ end process p_ran_gen;
burst_train <= '0';
end loop;
while t_sim2 < 800000 us loop
while t_sim2 < 50000 us loop
t_sim2 <= NOW - t_sim1;
if random_intervals then
interval := rand_num * 1 ns;
......
......@@ -91,17 +91,15 @@ architecture behav of testbench is
-- Number of I2C masters and slaves for the I2C bus model
constant c_nr_masters : positive := 1;
constant c_nr_slaves : positive := 1;
--Activate randomly spaced input pulses
constant random_intervals : boolean := false; --fixed interval when false, random interval when true.
--============================================================================
-- Component declarations
--============================================================================
component conv_ttl_blo is
-- generic
-- (
-- g_nr_ttl_chan : natural := 6;
-- g_nr_inv_chan : natural := 4;
-- g_sim : boolean := false
-- );
port
(
-- Clocks
......@@ -390,7 +388,7 @@ begin
ttl_n_i => ttl_inp_n,
ttl_o => ttl_outp,
inv_n_i => inv_inp_n,--DB changed from '1's and open
inv_n_i => inv_inp_n,
inv_o => inv_outp,
blo_i => blo_inp,
......@@ -496,9 +494,9 @@ begin
-- Random number generator
--============================================================================
p_ran_gen : process
variable seed1, seed2: positive := 1; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10000.0; -- the range of random values created will be 0 to +1000.
variable seed1, seed2: positive := 1; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10000.0; -- the range of random values created will be 0 to +1000.
begin
uniform(seed1, seed2, rand); -- generate random number
......@@ -512,7 +510,7 @@ end process p_ran_gen;
--============================================================================
blo_inp(6) <= '0';
-- gen_pulse_chain : for i in 6 downto 2 generate
-- blo_inp(i) <= blo_outp(i); --DB was blo_inp(i-1)
-- blo_inp(i) <= blo_outp(i);
-- end generate gen_pulse_chain;
inv_inp_n <= not inv_inp; --This line is to recover from the inverting buffer which exists on the board
......@@ -523,38 +521,45 @@ end process p_ran_gen;
begin
ttl_inp_n(6 downto 1) <= (others => '1'); ---DB was others set to 1
inv_inp (4 downto 1) <= (others => '0'); ---DB
blo_inp(6 downto 1) <= (others => '0'); ---DB new line to remove all blo stimulus
ttl_inp_n(6 downto 1) <= (others => '1');
inv_inp (4 downto 1) <= (others => '0');
blo_inp(6 downto 1) <= (others => '0');
wait until inv_flag_n = true;
while (inv_flag_n = true) loop
--interval := rand_num * 1 ns;
interval := 250 ns;
--for j in 6 downto 1 loop
ttl_inp_n(1) <= '1';
if random_intervals then
interval := rand_num * 1 ns;
if interval < 250 ns then
interval := 250 ns;
end if;
else
interval := 250 ns;--changes pulse frequency
end if;
--Activate for loop if all channels should be tested
for j in 1 downto 1 loop --change loop counter range to change number of channels to be tested
ttl_inp_n(j) <= '1'; --testing only channel 1
wait for interval;
ttl_inp_n(1) <= '0';
ttl_inp_n(j) <= '0';
wait for 250 ns;
ttl_inp_n(1) <= '1';
if ttl_outp(1) /= '1' then
ttl_inp_n(j) <= '1';
if ttl_outp(j) /= '1' then
assert false report "ttl_outp not '1'" severity warning;
end if;
if blo_outp(1) /= '1' then
if blo_outp(j) /= '1' then
assert false report "blo_outp not '1'" severity warning;
end if;
-- blo_inp(j) <= '0';
-- wait for 10 us;
-- blo_inp(j) <= '1';
-- wait for 1 us;
-- blo_inp(j) <= '0';
-- if ttl_outp(j) /= '1' then
-- assert false report "ttl_outp not '1'" severity warning;
-- end if;
-- if blo_outp(6) /= '1' then
-- assert false report "blo_outp not '1'" severity warning;
-- end if;
--end loop;
--blo_inp(j) <= '0';
--wait for 10 us;
--blo_inp(j) <= '1';
--wait for 1 us;
--blo_inp(j) <= '0';
if ttl_outp(j) /= '1' then
assert false report "ttl_outp not '1'" severity warning;
end if;
--if blo_outp(j) /= '1' then
-- assert false report "blo_outp not '1'" severity warning;
--end if;
end loop;
......@@ -569,20 +574,21 @@ end process p_ran_gen;
end if;
wait for 50 ns;
inv_inp(j) <= '0';
-- if blo_outp(6) /= '1' then
-- assert false report "blo_outp not '1'" severity warning;
-- end if;
if blo_outp(6) /= '1' then
assert false report "blo_outp not '1'" severity warning;
end if;
end loop;
end loop;
end loop;
end process p_stim_pulse;
process
begin
inv_flag_n <= true;
wait for 20 ms; --DB originally 2ms
wait for 50 ms;
inv_flag_n <= false;
wait for 50 ms; ---DB originally 500ms
wait for 50 ms;
inv_flag_n <= true;
wait for 10 ms;
inv_flag_n <= false;
......
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