Commit 655fa773 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Add and change information for v2.1 gateware

parent 3b4a2796
...@@ -9,9 +9,9 @@ ...@@ -9,9 +9,9 @@
\noindent \rule{\textwidth}{.1cm} \noindent \rule{\textwidth}{.1cm}
\hfill Gateware v2.0 \hfill Gateware v2.1
\hfill March 26, 2014 \hfill April 8, 2014
\vspace*{3cm} \vspace*{3cm}
......
\subsection{Converter board registers} \subsection{Converter board registers}
\label{subsec:wbgen:reg} \label{app:conv-regs}
Base address: 0xf{}f{}f{}f{}f{}f{}f{}f Base address: 0x000
{ {
\rowcolors{2}{white}{gray!25} \rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}} \begin{longtable}{l l l p{.5\textwidth}}
...@@ -16,26 +16,30 @@ Base address: 0xf{}f{}f{}f{}f{}f{}f{}f ...@@ -16,26 +16,30 @@ Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
\hline \hline
\endfoot \endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\ 0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & 0xf{}f{}f{}f{}f{}f{}f{}f & SR & Status Register\\ 0x4 & (1) & SR & Status Register\\
0x8 & 0xf{}f{}f{}f{}f{}f{}f{}f & CR & Control Register\\ 0x8 & 0x00000000 & CR & Control Register\\
0xc & 0xf{}f{}f{}f{}f{}f{}f{}f & CH1PCR & Channel 1 Pulse Counter Register\\ 0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH2PCR & Channel 2 Pulse Counter Register\\ 0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH3PCR & Channel 3 Pulse Counter Register\\ 0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH4PCR & Channel 4 Pulse Counter Register\\ 0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0xf{}f{}f{}f{}f{}f{}f{}f & CH5PCR & Channel 5 Pulse Counter Register\\ 0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0xf{}f{}f{}f{}f{}f{}f{}f & CH6PCR & Channel 6 Pulse Counter Register\\ 0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0xf{}f{}f{}f{}f{}f{}f{}f & TVLR & Time Value Low Register\\ 0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0xf{}f{}f{}f{}f{}f{}f{}f & TVHR & Time Value High Register\\ 0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0xf{}f{}f{}f{}f{}f{}f{}f & TBMR & Tag Buffer Meta Register\\ 0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x30 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBCYR & Tag Buffer Cycles Register\\ 0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBTLR & Tag Buffer TAI Low Register\\ 0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0xf{}f{}f{}f{}f{}f{}f{}f & TBTHR & Tag Buffer TAI High Register\\ 0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0xf{}f{}f{}f{}f{}f{}f{}f & TBCSR & Tag Buffer Control and Status Register\\ 0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
\end{longtable} \end{longtable}
} }
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\vspace{11pt} \vspace{11pt}
\subsubsection{BIDR -- Board ID Register} \subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -74,6 +78,7 @@ Reset value: 0x54424c4f ...@@ -74,6 +78,7 @@ Reset value: 0x54424c4f
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{SR -- Status Register} \subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -104,14 +109,14 @@ Reset value: 0x54424c4f ...@@ -104,14 +109,14 @@ Reset value: 0x54424c4f
GWVERS GWVERS
} [\emph{read-only}]: Gateware version } [\emph{read-only}]: Gateware version
\\ \\
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x1e -- v1.14 \\ 0x20 -- v2.0 Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x2e -- v2.14
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
SWITCHES SWITCHES
} [\emph{read-only}]: Status of on-board switches } [\emph{read-only}]: Status of on-board switches (see Section~\ref{sec:switches})
\\ \\
0 -- switch is ON \\ 1 -- switch is OFF \\ bit 0 -- SW1.1 \\ bit 1 -- SW1.2 \\ ... \\ bit 4 -- SW2.1 \\ ... \\ bit 7 -- SW2.4 0 -- switch is ON \\ 1 -- switch is OFF
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
...@@ -123,7 +128,7 @@ RTM ...@@ -123,7 +128,7 @@ RTM
\item \begin{small} \item \begin{small}
{\bf {\bf
I2C\_WDTO I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error } [\emph{read/write}]: Communication watchdog timer status
\\ \\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it 1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small} \end{small}
...@@ -139,14 +144,14 @@ WRPRES ...@@ -139,14 +144,14 @@ WRPRES
I2C\_ERR I2C\_ERR
} [\emph{read/write}]: I2C communication error } [\emph{read/write}]: I2C communication error
\\ \\
1 -- attempted to address non-existing address \\ 0 -- idle 1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
PMISSE PMISSE
} [\emph{read/write}]: Pulse missed error } [\emph{read/write}]: Pulse missed error
\\ \\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle 1 -- input pulse rejected to safeguard blocking output stage \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small} \end{small}
\item \begin{small} \item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
...@@ -154,6 +159,7 @@ PMISSE ...@@ -154,6 +159,7 @@ PMISSE
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CR -- Control Register} \subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -206,6 +212,7 @@ Write the following sequence to trigger a pulse: \\ 0xde -- ...@@ -206,6 +212,7 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register} \subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\label{app:conv-regs-ch1pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -242,6 +249,7 @@ CH1PCR ...@@ -242,6 +249,7 @@ CH1PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register} \subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\label{app:conv-regs-ch2pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -278,6 +286,7 @@ CH2PCR ...@@ -278,6 +286,7 @@ CH2PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register} \subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\label{app:conv-regs-ch3pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -314,6 +323,7 @@ CH3PCR ...@@ -314,6 +323,7 @@ CH3PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register} \subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\label{app:conv-regs-ch4pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -350,6 +360,7 @@ CH4PCR ...@@ -350,6 +360,7 @@ CH4PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register} \subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\label{app:conv-regs-ch5pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -386,6 +397,7 @@ CH5PCR ...@@ -386,6 +397,7 @@ CH5PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register} \subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\label{app:conv-regs-ch6pcr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -422,6 +434,7 @@ CH6PCR ...@@ -422,6 +434,7 @@ CH6PCR
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register} \subsubsection{TVLR -- Time Value Low Register}
\label{app:conv-regs-tvlr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -460,6 +473,7 @@ Writing this field resets the internal cycles counter. ...@@ -460,6 +473,7 @@ Writing this field resets the internal cycles counter.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TVHR -- Time Value High Register} \subsubsection{TVHR -- Time Value High Register}
\label{app:conv-regs-tvhr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -498,6 +512,7 @@ Writing this field resets the internal cycles counter. ...@@ -498,6 +512,7 @@ Writing this field resets the internal cycles counter.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBMR -- Tag Buffer Meta Register} \subsubsection{TBMR -- Tag Buffer Meta Register}
\label{app:conv-regs-tbmr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -540,9 +555,13 @@ WRTAG ...@@ -540,9 +555,13 @@ WRTAG
\item \begin{small} \item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBCYR -- Tag Buffer Cycles Register} \subsubsection{TBCYR -- Tag Buffer Cycles Register}
\label{app:conv-regs-tbcyr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -581,6 +600,7 @@ Value of the 8-ns cycles counter when time tag was taken. ...@@ -581,6 +600,7 @@ Value of the 8-ns cycles counter when time tag was taken.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBTLR -- Tag Buffer TAI Low Register} \subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\label{app:conv-regs-tbtlr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -619,8 +639,9 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken. ...@@ -619,8 +639,9 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{itemize} \end{itemize}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register} \subsubsection{TBTHR -- Tag Buffer TAI High Register}
\label{app:conv-regs-tbthr}
\vspace{11pt} %\vspace{11pt}
\noindent \noindent
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\subsubsection{TBCSR -- Tag Buffer Control and Status Register} \subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\label{app:conv-regs-tbcsr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -706,7 +728,7 @@ EMPTY ...@@ -706,7 +728,7 @@ EMPTY
\item \begin{small} \item \begin{small}
{\bf {\bf
CLR CLR
} [\emph{read/write}]: Clear tag buffer } [\emph{write-only}]: Clear tag buffer
\\ \\
1 -- clear\\ 0 -- no effect 1 -- clear\\ 0 -- no effect
\end{small} \end{small}
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......
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...@@ -66,8 +66,9 @@ ...@@ -66,8 +66,9 @@
14-02-2014 & 2.00 & Version 2.0 of gateware, with diagnostics support including: unique board ID 14-02-2014 & 2.00 & Version 2.0 of gateware, with diagnostics support including: unique board ID
and temperature readout, input pulse counters, pulse time-tagging and and temperature readout, input pulse counters, pulse time-tagging and
manual pulse triggering. \\ manual pulse triggering. \\
26-03-2014 & 2.10 & Version 2.1 of gateware, bringing down the max. allowed pulse frequency 08-04-2014 & 2.10 & Version 2.1 of gateware, bringing down the max. allowed input pulse frequency,
to 1.6~kHz and changing the pulse timetag FIFO for a timetag buffer\\ changing the ERR LED behaviour, adding system errors and changing the pulse
timetag FIFO for a timetag ring buffer \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -314,46 +315,7 @@ FPGA architecture is not guaranteed to provide the same results. The \textit{res ...@@ -314,46 +315,7 @@ FPGA architecture is not guaranteed to provide the same results. The \textit{res
module has an initial value set for the counter signal after power-up, which is guaranteed module has an initial value set for the counter signal after power-up, which is guaranteed
by XST to be set after the FPGA's GSR signal is de-asserted. by XST to be set after the FPGA's GSR signal is de-asserted.
By default, the reset time is set to 100~$ms$. By default, the reset time is set to 100~ms.
%==============================================================================
% SEC: RTM detection
%==============================================================================
\pagebreak
\section{RTM detection}
\label{sec:rtm-detect}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{rtm\_detector} & \\
\textbf{Ports} & \textit{rtmm\_i(2..0)} & RTM mainboard detection lines \\
& \textit{rtmp\_i(2..0)} & RTM piggyback detection lines \\
& \textit{rtmm\_ok\_o} & RTM mainboard present \\
& \textit{rtmp\_ok\_o} & RTM piggyback present \\
\textbf{Usage} & Light ERR status LED & \\
\hline
\end{tabular}
}
\vspace*{11pt}
RTM detection is described in \cite{rtm-det}. Since an RTMM/P missing would mean
all \textit{rtmm\_i}/\textit{rtmp\_i} lines are all-ones, the \textit{rtm\_detector}
module sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the
\textit{rtmm\_i} and \textit{rtmp\_i} input signals are respectively all-ones.
The \textit{rtmm\_ok} and \textit{rtmp\_ok} signals are NANDed together to light
the ERR status LED on the CONV-TTL-BLO. The status of the RTM detection lines
can also be read via their respective fields in the converter board status register
(SR -- see Appendix~\ref{app:conv-regs-sr}).
\begin{figure}[h]
\centerline{\includegraphics[width=.76\textwidth]{fig/rtm-detect}}
\caption{\textit{rtm\_detector} block in CONV-TTL-BLO gateware}
\label{fig:rtm-detect}
\end{figure}
%============================================================================== %==============================================================================
% SEC: Bicolor LEDs % SEC: Bicolor LEDs
...@@ -493,6 +455,7 @@ selection signals to these multiplexers are set throughout the logic. ...@@ -493,6 +455,7 @@ selection signals to these multiplexers are set throughout the logic.
& \textit{en\_i} & Pulse generator enable \\ & \textit{en\_i} & Pulse generator enable \\
& \textit{gf\_en\_n\_i} & Active-low glitch filter enable \\ & \textit{gf\_en\_n\_i} & Active-low glitch filter enable \\
& \textit{trig\_a\_i} & Pulse trigger \\ & \textit{trig\_a\_i} & Pulse trigger \\
& \textit{pulse\_err\_p\_o} & Pulse error \\
& \textit{pulse\_o} & Pulse output \\ & \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~$\mu$s pulses with min. period of 6~$\mu$s \\ \textbf{Usage} & Output pulse & 1.2~$\mu$s pulses with min. period of 6~$\mu$s \\
& & and one-cycle wide glitch filter \\ & & and one-cycle wide glitch filter \\
...@@ -574,6 +537,13 @@ is in this rejection state, they are not replicated at the output. The pulse rej ...@@ -574,6 +537,13 @@ is in this rejection state, they are not replicated at the output. The pulse rej
phase lasts for \textit{g\_duty\_cycle\_div}*\textit{g\_pwidth}, yielding a maximum duty phase lasts for \textit{g\_duty\_cycle\_div}*\textit{g\_pwidth}, yielding a maximum duty
cycle of 1/\textit{g\_duty\_cycle\_div} for input pulses. cycle of 1/\textit{g\_duty\_cycle\_div} for input pulses.
Should a pulse rising-edge arrive anywhere within the generation or rejection phase
in the FSM, the \textit{pulse\_err\_p\_o} output is set high for one clock cycle. This
signal can be used to, e.g., count the number of pulses that were rejected on a board. In
the actual top-level design, however, missed pulse counting is not implemented, the
\textit{pulse\_err\_p\_o} output simply asserts the SR.PMISSE bit (see
Appendix~\ref{app:conv-regs-sr}).
Note that due to the fact that the counter starts counting up from zero and delays Note that due to the fact that the counter starts counting up from zero and delays
in the glitch filter when it is enabled, the maximum value of the internal counter is not in the glitch filter when it is enabled, the maximum value of the internal counter is not
\textit{g\_pwidth}. Instead, the counter counts up to a pair of VHDL constants defined \textit{g\_pwidth}. Instead, the counter counts up to a pair of VHDL constants defined
...@@ -905,7 +875,6 @@ The folder structure for the project is presented below. ...@@ -905,7 +875,6 @@ The folder structure for the project is presented below.
\end{itemize} \end{itemize}
\item conv\_pulse\_gen.vhd \item conv\_pulse\_gen.vhd
\item reset\_gen.vhd \item reset\_gen.vhd
\item rtm\_detector.vhd
\end{itemize} \end{itemize}
\item sim/ \item sim/
\item syn/ \item syn/
...@@ -1052,9 +1021,6 @@ top-level file. ...@@ -1052,9 +1021,6 @@ top-level file.
Status LEDs & -- \textit{bicolor\_led\_ctrl} instantiation \newline Status LEDs & -- \textit{bicolor\_led\_ctrl} instantiation \newline
-- connecting the \textit{led\_state\_i} input of the -- connecting the \textit{led\_state\_i} input of the
component to the relevant control signals \\ component to the relevant control signals \\
RTM detection & -- inverting the input signals from the RTM detection lines \newline
-- \textit{rtm\_detector} component instantiation \\
\end{longtable} \end{longtable}
} % end rowcolors } % end rowcolors
......
...@@ -32,8 +32,7 @@ peripheral { ...@@ -32,8 +32,7 @@ peripheral {
Rightmost nibble hex value is minor release decimal value \ Rightmost nibble hex value is minor release decimal value \
e.g. \ e.g. \
0x11 -- v1.1 \ 0x11 -- v1.1 \
0x1e -- v1.14 \ 0x2e -- v2.14";
0x20 -- v2.0";
prefix = "gwvers"; prefix = "gwvers";
type = SLV; type = SLV;
size = 8; size = 8;
...@@ -43,12 +42,7 @@ peripheral { ...@@ -43,12 +42,7 @@ peripheral {
field { field {
name = "Status of on-board switches"; name = "Status of on-board switches";
description = "0 -- switch is ON \ description = "0 -- switch is ON \
1 -- switch is OFF \ 1 -- switch is OFF";
bit 0 -- SW1.1 \