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Conv TTL Blocking - Gateware
Commit 63d84121 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Changes to hdl guide for release 4

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doc/hdlg/cern-title.tex
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...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
\hfill Gateware v3.0 \hfill Gateware v3.0
\hfill January 27, 2015 \hfill February 17, 2017
\vspace*{3cm} \vspace*{3cm}
...@@ -26,8 +26,8 @@ ...@@ -26,8 +26,8 @@
%--------------------------------------------------------------- %---------------------------------------------------------------
% name % name
%--------------------------------------------------------------- %---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}} \noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
\noindent { \textit {Last modified by Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}\\
\noindent \rule{\textwidth}{.05cm} \noindent \rule{\textwidth}{.05cm}
\end{titlepage} \end{titlepage}
doc/hdlg/conv-regs.tex
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doc/hdlg/fig/block-diagram.svg
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doc/hdlg/hdlg-conv-ttl-blo.tex
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...@@ -85,6 +85,7 @@ work, see \\ ...@@ -85,6 +85,7 @@ work, see \\
25-09-2014 & 3.00 & Version 3.0 of gateware, using the new converter board common gateware~\cite{conv-common-gw-ohwr} \newline 25-09-2014 & 3.00 & Version 3.0 of gateware, using the new converter board common gateware~\cite{conv-common-gw-ohwr} \newline
\textbf{This version changes the memory map} \\ \textbf{This version changes the memory map} \\
27-01-2015 & 3.01 & Added repository download commands to Section~\ref{sec:intro} \\ 27-01-2015 & 3.01 & Added repository download commands to Section~\ref{sec:intro} \\
17-02-2017 & 4.00 & Version 4 modifications, moved LED logic inside the common gateware entity \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -262,8 +263,29 @@ shown in Figure~\ref{fig:switches}. ...@@ -262,8 +263,29 @@ shown in Figure~\ref{fig:switches}.
\end{figure} \end{figure}
\pagebreak \pagebreak
%==============================================================================
% SEC: PCB Version
%==============================================================================
\subsection{PCB Version}
\label{sec:pcb-ver}
CONV-TTL-BLO boards from version 4 onwards, offer the possibility for the FPGA to receive
information on the hardware version. This information is hardwired on the board in the form of
pulled-up or pulled-down resistors for each bit ~\cite{conv-ttl-blo-hwguide}.
As gateware release 4 together with hardware version 4, enables pulse repetition at higher
frequencies~\cite{conv-ttl-blo-ug}. Therefore, PCB version input lines are used to enable the so-
called \textit{burst mode} enable signal, needed by conv-common-gw component in order to enable pulse
width selection and burst mode functionality.
The PCB version I/O is therefore checked, burst mode is enabled via a comparator. if the version is 4 or higher.
The functionality is disabled for older PCBs\footnotemark\footnotetext{Since the hardware version is
not available on older boards and since the I/O pins now assigned to it were by default pulled-
down, board v3 and earlier will show the PCB version as 0)}.
\section{Output logic} \section{Output logic}
%============================================================================== %==============================================================================
% SEC: TTL/TTL-BAR output logic % SEC: TTL/TTL-BAR output logic
%============================================================================== %==============================================================================
...@@ -344,7 +366,7 @@ $reg. index = \frac{addr}{4} + 1$ ...@@ -344,7 +366,7 @@ $reg. index = \frac{addr}{4} + 1$
\hline \hline
Board registers & 0x000 & 0x0ff & Coverter board registers \\ Board registers & 0x000 & 0x0ff & Coverter board registers \\
MultiBoot & 0x100 & 0x11f & MultiBoot module \\ MultiBoot & 0x100 & 0x11f & MultiBoot module \\
One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\ %One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
SDB descriptor & 0xf00 & 0xfff & SDB descriptor (see~\cite{sdb}) \\ SDB descriptor & 0xf00 & 0xfff & SDB descriptor (see~\cite{sdb}) \\
\hline \hline
\end{tabular} \end{tabular}
......
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