1 bit per RTM output channel \\ 1 -- line active \\ 0 -- line inactive
\end{small}
\item\begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
HWVERS
} [\emph{read-only}]: Hardware version
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
PCB version - Hardwired on the board \\ Only meaningful for HW v4.0 and over \\ Earlier versions show 0. The register \\ uses 4 bits for the version number and\\ 2 bits for the execution.\\ e.g. \\ 0x010001 -- hw v4.1 \\ 0x010111 -- hw v5.3 \\ 0x00-- hw v3 and earlier
\end{small}
\item\begin{small}
{\bf
...
...
@@ -163,6 +182,42 @@ WRPRES
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item\begin{small}
{\bf
I2C\_ERR
...
...
@@ -172,19 +227,21 @@ I2C\_ERR
\end{small}
\item\begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
FLIM\_PMISSE
} [\emph{read/write}]: Frequency error
\\
1 -- pulse arrived during pulse rejection phase\\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
1 -- Input above maximum supported frequency\\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\item\begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
{\bf
FWDG\_PMISSE
} [\emph{read/write}]: Frequency watchdog error
\\
1 -- Pulse over maximum pulse count for given frequency' \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\subsubsection{CR - Control Register}
\label{app:conv-regs-CR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
...
...
@@ -219,7 +276,7 @@ RST\_UNLOCK
\item\begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
} [\emph{read/write}]: Reset bit - active only if RST_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
...
...
@@ -234,29 +291,28 @@ Write the following sequence to trigger a pulse: \\ 0xde --
\textbf{Unimplemented bits}: write as '0', read undefined
