Commit 5e1ddca0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Preparing for new folder structure

This commit: trying .gise in .gitignore
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 08c03415
...@@ -9,12 +9,12 @@ ...@@ -9,12 +9,12 @@
-- --
-- version: 1.0 -- version: 1.0
-- --
-- description: -- description:
-- --
-- dependencies: -- dependencies:
-- --
-- references: -- references:
-- --
--============================================================================== --==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
--============================================================================== --==============================================================================
...@@ -31,13 +31,14 @@ ...@@ -31,13 +31,14 @@
-- last changes: -- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created -- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--============================================================================== --==============================================================================
-- TODO: - -- TODO: -
--============================================================================== --==============================================================================
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity glitch_filt is entity glitch_filt is
generic generic
...@@ -52,7 +53,7 @@ entity glitch_filt is ...@@ -52,7 +53,7 @@ entity glitch_filt is
( (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
-- Data input -- Data input
dat_i : in std_logic; dat_i : in std_logic;
...@@ -65,11 +66,30 @@ end entity glitch_filt; ...@@ -65,11 +66,30 @@ end entity glitch_filt;
architecture behav of glitch_filt is architecture behav of glitch_filt is
--============================================================================
-- Component declarations
--============================================================================
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component gc_sync_ffs;
--============================================================================ --============================================================================
-- Signal declarations -- Signal declarations
--============================================================================ --============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0); signal glitch_filt : std_logic_vector(g_len downto 0);
signal degl_dat : std_logic; signal dat_synced : std_logic;
--============================================================================== --==============================================================================
-- architecture begin -- architecture begin
...@@ -79,8 +99,20 @@ begin ...@@ -79,8 +99,20 @@ begin
--============================================================================ --============================================================================
-- Glitch filtration logic -- Glitch filtration logic
--============================================================================ --============================================================================
-- First, assign the current sample of the glitch filter -- First, synchronize the data input in the clk_i domain
glitch_filt(0) <= dat_i; cmp_sync : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => dat_i,
synced_o => dat_synced,
npulse_o => open,
ppulse_o => open
);
-- Then, assign the current sample of the glitch filter
glitch_filt(0) <= dat_synced;
-- Generate glitch filter FFs when the filter length is > 0 -- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate gen_glitch_filt: if (g_len > 0) generate
......
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project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
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project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
This diff is collapsed.
...@@ -146,6 +146,9 @@ ...@@ -146,6 +146,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -302,6 +305,7 @@ ...@@ -302,6 +305,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
......
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
...@@ -49,12 +49,12 @@ entity conv_ttl_blo is ...@@ -49,12 +49,12 @@ entity conv_ttl_blo is
g_nr_ttl_chan : natural := 6; g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4 g_nr_inv_chan : natural := 4
); );
port port
( (
-- Clock lines -- Clock lines
fpga_clk_p_i : in std_logic; --Using the 125MHz clock fpga_clk_p_i : in std_logic; --Using the 125MHz clock
fpga_clk_n_i : in std_logic; fpga_clk_n_i : in std_logic;
-- LEDs -- LEDs
led_ctrl0_o : out std_logic; led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic; led_ctrl0_oen_o : out std_logic;
...@@ -66,7 +66,7 @@ entity conv_ttl_blo is ...@@ -66,7 +66,7 @@ entity conv_ttl_blo is
led_wr_link_syserror_o : out std_logic; led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic; led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic; led_wr_ownaddr_i2c_o : out std_logic;
-- Lines for the i2c_slave -- Lines for the i2c_slave
scl_i : in std_logic; scl_i : in std_logic;
scl_o : out std_logic; scl_o : out std_logic;
...@@ -140,7 +140,7 @@ architecture behav of conv_ttl_blo is ...@@ -140,7 +140,7 @@ architecture behav of conv_ttl_blo is
end component reset_gen; end component reset_gen;
-- I2C bridge -- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers) -- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is component vbcp_wb is
port port
( (
...@@ -158,8 +158,8 @@ architecture behav of conv_ttl_blo is ...@@ -158,8 +158,8 @@ architecture behav of conv_ttl_blo is
-- I2C address and status -- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0); i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic; tip_o : out std_logic;
i2c_err_o : out std_logic; err_o : out std_logic;
-- Wishbone master signals -- Wishbone master signals
wbm_stb_o : out std_logic; wbm_stb_o : out std_logic;
...@@ -174,7 +174,7 @@ architecture behav of conv_ttl_blo is ...@@ -174,7 +174,7 @@ architecture behav of conv_ttl_blo is
wbm_err_i : in std_logic wbm_err_i : in std_logic
); );
end component vbcp_wb; end component vbcp_wb;
--============================================================================ --============================================================================
-- Signal declarations -- Signal declarations
--============================================================================ --============================================================================
...@@ -189,7 +189,7 @@ architecture behav of conv_ttl_blo is ...@@ -189,7 +189,7 @@ architecture behav of conv_ttl_blo is
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0); signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0); signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0); signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals -- RAM signals
signal ram_we : std_logic; signal ram_we : std_logic;
signal ram_ack : std_logic; signal ram_ack : std_logic;
...@@ -198,8 +198,8 @@ architecture behav of conv_ttl_blo is ...@@ -198,8 +198,8 @@ architecture behav of conv_ttl_blo is
signal bicolor_led_state : std_logic_vector(23 downto 0); signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals -- I2C bridge signals
signal i2c_done : std_logic; signal vbcp_done : std_logic;
signal i2c_err : std_logic; signal vbcp_err : std_logic;
signal i2c_err_led : std_logic; signal i2c_err_led : std_logic;
signal i2c_up : std_logic; signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0); signal i2c_addr : std_logic_vector(6 downto 0);
...@@ -207,19 +207,19 @@ architecture behav of conv_ttl_blo is ...@@ -207,19 +207,19 @@ architecture behav of conv_ttl_blo is
signal led_i2c_clkdiv : unsigned(22 downto 0); signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0); signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic; signal blink_state : std_logic;
begin begin
--============================================================================ --============================================================================
-- Generate 125 MHz global signal from differential lines -- Generate 125 MHz global signal from differential lines
--============================================================================ --============================================================================
cmp_125_diff_buf : IBUFGDS cmp_125_diff_buf : IBUFGDS
generic map generic map
( (
DIFF_TERM => TRUE, DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE IBUF_LOW_PWR => TRUE
) )
port map port map
( (
I => fpga_clk_p_i, I => fpga_clk_p_i,
IB => fpga_clk_n_i, IB => fpga_clk_n_i,
...@@ -242,7 +242,7 @@ begin ...@@ -242,7 +242,7 @@ begin
rst_i => '0', rst_i => '0',
rst_n_o => rst_n rst_n_o => rst_n
); );
-- rst <= not rst_n; -- rst <= not rst_n;
mr_n_o <= rst_n; mr_n_o <= rst_n;
...@@ -251,7 +251,7 @@ begin ...@@ -251,7 +251,7 @@ begin
--============================================================================ --============================================================================
-- Set the I2C address signal according to ELMA protocol [1] -- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i; i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component -- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb cmp_i2c_bridge : vbcp_wb
port map port map
...@@ -270,8 +270,8 @@ begin ...@@ -270,8 +270,8 @@ begin
-- I2C address and status -- I2C address and status
i2c_addr_i => i2c_addr, i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done, tip_o => vbcp_done,
i2c_err_o => i2c_err, err_o => vbcp_err,
-- Wishbone master signals -- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb, wbm_stb_o => xbar_slave_in(0).stb,
...@@ -285,8 +285,8 @@ begin ...@@ -285,8 +285,8 @@ begin
wbm_rty_i => xbar_slave_out(0).rty, wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err wbm_err_i => xbar_slave_out(0).err
); );
-- Process to blink the LED for a finite amount of time when the i2c_done -- Process to blink the LED for a finite amount of time when the vbcp_done
-- signal is set. -- signal is set.
p_i2c_blink : process(clk125) p_i2c_blink : process(clk125)
begin begin
...@@ -301,7 +301,7 @@ begin ...@@ -301,7 +301,7 @@ begin
when '0' => when '0' =>
led_i2c <= '0'; led_i2c <= '0';
if (i2c_done = '1') then if (vbcp_done = '1') then
blink_state <= '1'; blink_state <= '1';
end if; end if;
...@@ -333,7 +333,7 @@ begin ...@@ -333,7 +333,7 @@ begin
if rising_edge(clk125) then if rising_edge(clk125) then
if (rst_n = '0') then if (rst_n = '0') then
i2c_err_led <= '0'; i2c_err_led <= '0';
elsif (i2c_err = '1') then elsif (vbcp_err = '1') then
i2c_err_led <= '1'; i2c_err_led <= '1';
end if; end if;
end if; end if;
...@@ -406,7 +406,7 @@ begin ...@@ -406,7 +406,7 @@ begin
--============================================================================ --============================================================================
-- Bicolor LED matrix logic -- Bicolor LED matrix logic
--============================================================================ --============================================================================
-- Bicolor LED controls, corresponding to the column orders on the -- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit. -- bicolor_led_ctrl unit.
-- WR address -- WR address
...@@ -443,7 +443,7 @@ begin ...@@ -443,7 +443,7 @@ begin
bicolor_led_state(19 downto 18) <= c_LED_GREEN; bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2 -- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF; bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3 -- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF; bicolor_led_state(23 downto 22) <= c_LED_OFF;
......
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...@@ -70,9 +70,10 @@ package i2c_slave_pkg is ...@@ -70,9 +70,10 @@ package i2c_slave_pkg is
i2c_addr_i : in std_logic_vector(6 downto 0); i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1' -- ACK input, should be set after done_p_o = '1'
-- '0' - ACK -- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - NACK -- '1' - ACK
ack_n_i : in std_logic; -- '0' - NACK
i2c_ack_i : in std_logic;
-- I2C bus operation, set after address detection -- I2C bus operation, set after address detection
-- '0' - write -- '0' - write
......
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