Commit 5dcc4b58 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

hdl: Fixed a problem with the pulse counters

When the TTL selection switch is set for TTL-BAR signals, the pulse counters
were starting from the value 1. This was because the input channel is
first sent through a synchronizer FF chain, which was reset by the
same reset signal as the rest of the logic.

Due to the reset pulse inside the logic and the fact that when the TTL switch
is set to TTL-BAR, a non-existing signal represents a high level, this
high level was detected (due to the sync FF chain) only after the reset pulse.
This resulted in a rising edge on the trigger signal, which resulted in the
pulse counters incrementing to '1' on every reset.

This problem has been solved by not resetting the sync FF chain.
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent a9306cba
......@@ -745,31 +745,10 @@ begin
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
fpga_oe_o <= '1';
fpga_blo_oe_o <= '1';
fpga_trig_ttl_oe_o <= '1';
fpga_inv_oe_o <= '1';
--============================================================================
-- TTL and blocking pulse generation logic
......@@ -810,13 +789,13 @@ begin
-----------------------------------------------------------------------------
-- Generate pulse repetition logic
-----------------------------------------------------------------------------
gen_ttl_pulse_generators : for i in 1 to g_nr_ttl_chan generate
gen_pulse_logic : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk20_vcxo_i domain
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk20_vcxo_i,
rst_n_i => rst_n,
rst_n_i => '1',
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_r_edge_p(i)
......@@ -840,13 +819,16 @@ begin
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
-- the mux input.
--
-- Counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption from the counter.
p_ttlbar_nosig : process(clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') or (fpga_input_ttl_n_i(i) = '0') then
ttlbar_nosig_n(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif (fpga_input_ttl_n_i(i) = '1') then
elsif (ttl_switch_n_i = '1') then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if (ttlbar_nosig_cnt(i) = 1999) then
ttlbar_nosig_n(i) <= '0';
......@@ -873,14 +855,9 @@ begin
pulse_o => pulse_outp(i)
);
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse_outp when (ttl_switch_n_i = '0') else
not pulse_outp;
fpga_trig_blo_o <= pulse_outp;
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led : process (clk20_vcxo_i, rst_n) is
p_pulse_led : process (clk20_vcxo_i) is
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
......@@ -907,14 +884,17 @@ begin
end if;
end if;
end process;
end generate gen_ttl_pulse_generators;
end generate gen_pulse_logic;
-----------------------------------------------------------------------------
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse_outp when (ttl_switch_n_i = '0') else
not pulse_outp;
fpga_trig_blo_o <= pulse_outp;
-- Pulse status LED output assignments
pulse_front_led_n_o <= (not pulse_leds) when (ttl_oe = '1') else
(others => '1');
pulse_rear_led_n_o <= (not pulse_leds) when (blo_oe = '1') else
(others => '1');
pulse_front_led_n_o <= not pulse_leds;
pulse_rear_led_n_o <= not pulse_leds;
-- General-purpose INV TTL outputs
inv_out_o <= inv_in_n_i;
......
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