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Conv TTL Blocking - Gateware
Commit 5b6e568a authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Working on integrating multiboot module 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 92c9d25a
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Showing with 246 additions and 380 deletions
hdl/multiboot/Manifest.py 0 → 100644
View file @ 5b6e568a
modules = {"local" : "rtl"}
hdl/multiboot/rtl/Manifest.py
View file @ 5b6e568a
......@@ -2,6 +2,5 @@ files = [
"multiboot_regs.vhd",
"multiboot_fsm.vhd",
"spi_master.vhd",
"m25p_flash.vhd",
"xil_multiboot.vhd"
]
hdl/multiboot/rtl/xil_multiboot.vhd
View file @ 5b6e568a
......@@ -51,8 +51,8 @@ entity xil_multiboot is
rst_n_i : in std_logic;
-- Wishbone ports
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
......@@ -237,26 +237,21 @@ begin
--============================================================================
-- Register component instantiation
--============================================================================
-- First, some unused signal assignments
wb_o.err <= '0';
wb_o.rty <= '0';
-- Now, instantiate the component
cmp_regs : multiboot_regs
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_i.adr(4 downto 2),
wb_dat_i => wb_i.dat,
wb_dat_o => wb_o.dat,
wb_cyc_i => wb_i.cyc,
wb_sel_i => wb_i.sel,
wb_stb_i => wb_i.stb,
wb_we_i => wb_i.we,
wb_ack_o => wb_o.ack,
wb_stall_o => wb_o.stall,
wb_adr_i => wbs_i.adr(4 downto 2),
wb_dat_i => wbs_i.dat,
wb_dat_o => wbs_o.dat,
wb_cyc_i => wbs_i.cyc,
wb_sel_i => wbs_i.sel,
wb_stb_i => wbs_i.stb,
wb_we_i => wbs_i.we,
wb_ack_o => wbs_o.ack,
wb_stall_o => wbs_o.stall,
multiboot_cr_rdbootsts_o => rdbootsts,
multiboot_cr_iprog_o => iprog,
......
hdl/multiboot/syn/conv_ttl_blo.gise deleted 100644 → 0
View file @ 92c9d25a
This diff is collapsed.
hdl/multiboot/syn/run.tcl deleted 100644 → 0
View file @ 92c9d25a
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
hdl/release/rtl/conv_regs.vhd
View file @ 5b6e568a
......@@ -109,11 +109,12 @@ begin
when "10" =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
conv_regs_cr_rst_int <= wrdata_reg(31);
conv_regs_cr_rst_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
rddata_reg(31) <= conv_regs_cr_rst_int;
rddata_reg(1) <= 'X';
if (conv_regs_cr_rst_unlock_int = '1') then
rddata_reg(1) <= conv_regs_cr_rst_int;
end if;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
......@@ -143,6 +144,7 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......
hdl/release/syn/Makefile
View file @ 5b6e568a
......@@ -47,6 +47,10 @@ FILES := ../top/conv_ttl_blo.ucf \
../../vbcp_wb/rtl/vbcp_wb.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../multiboot/rtl/multiboot_regs.vhd \
../../multiboot/rtl/multiboot_fsm.vhd \
../../multiboot/rtl/spi_master.vhd \
../../multiboot/rtl/xil_multiboot.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
......
hdl/release/syn/conv_ttl_blo.gise
View file @ 5b6e568a
......@@ -52,6 +52,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
......@@ -62,6 +63,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
......@@ -72,35 +74,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471978" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853702" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376471999" xil_pn:in_ck="-159470544935230363" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376471978">
<transform xil_pn:end_ts="1381853724" xil_pn:in_ck="3190287689474023470" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1381853702">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +120,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1376471999" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1376471999">
<transform xil_pn:end_ts="1381853724" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1381853724">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376472010" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376471999">
<transform xil_pn:end_ts="1381853733" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1381853724">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +133,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1376472062" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376472010">
<transform xil_pn:end_ts="1381853789" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1381853733">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +146,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1376472115" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376472062">
<transform xil_pn:end_ts="1381853845" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1381853789">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +160,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1376472151" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376472115">
<transform xil_pn:end_ts="1381853881" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1381853845">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -170,7 +172,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1376472115" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376472104">
<transform xil_pn:end_ts="1381853845" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381853834">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo.xise
View file @ 5b6e568a
This diff is collapsed.
hdl/release/top/Manifest.py
View file @ 5b6e568a
......@@ -9,6 +9,7 @@ modules = {
"../rtl",
"../../vbcp_wb",
"../../ctb_pulse_gen",
"../../multiboot/",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../../../../ip_cores/general-cores"
......
hdl/release/top/conv_ttl_blo.ucf
View file @ 5b6e568a
......@@ -298,19 +298,18 @@ NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- ROM memory
###-----------------------------------------------------------------------------
#NET "fpga_prom_cclk_o" LOC = Y20;
#NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_cso_b_n_o" LOC = AA3;
#NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_miso_i" LOC = AA20;
#NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_mosi_o" LOC = AB20;
#NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
#
#
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
###=============================================================================
###-- WHITE RABBIT
###=============================================================================
......
hdl/release/top/conv_ttl_blo.vhd
View file @ 5b6e568a
......@@ -97,11 +97,16 @@ entity conv_ttl_blo is
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
......@@ -120,10 +125,11 @@ architecture behav of conv_ttl_blo is
-- Constant declarations
--============================================================================
-- Firmware version
constant c_fwvers : std_logic_vector(15 downto 0) := x"0102";
constant c_fwvers : std_logic_vector(15 downto 0) := x"0200";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 1;
constant c_nr_slaves : natural := 2;
-----------------------------------------
-- Memory map
......@@ -131,26 +137,32 @@ architecture behav of conv_ttl_blo is
-- * all registers are word-aligned
-----------------------------------------
-- CONV_REGS [000-040]
-- MULTIBOOT [040-080]
-----------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000040";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000FC0";
constant c_mask_multiboot : t_wishbone_address := x"00000FC0";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs
c_slv_conv_regs => c_addr_conv_regs,
c_slv_multiboot => c_addr_multiboot
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs
c_slv_conv_regs => c_mask_conv_regs,
c_slv_multiboot => c_mask_multiboot
);
--============================================================================
......@@ -211,34 +223,6 @@ architecture behav of conv_ttl_blo is
);
end component ctb_pulse_gen;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
component pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen_gp;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is
......@@ -274,7 +258,41 @@ architecture behav of conv_ttl_blo is
wbm_err_i : in std_logic
);
end component vbcp_wb;
-- Xilinx MultiBoot component
-- (use: remote reprogramming of the FPGA)
component xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xil_multiboot;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
-- Converter board control registers
component conv_regs is
port (
rst_n_i : in std_logic;
......@@ -307,7 +325,7 @@ architecture behav of conv_ttl_blo is
-- Signal declarations
--============================================================================
-- Clock signals
signal clk125 : std_logic;
signal clk125 : std_logic;
signal clk_50, clk_buf_50 : std_logic;
signal clk_200, clk_buf_200 : std_logic;
signal clk_250, clk_buf_250 : std_logic;
......@@ -326,15 +344,15 @@ architecture behav of conv_ttl_blo is
signal switches_n : std_logic_vector(7 downto 0);
-- Signals for pulse generation triggers
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl_a, trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_ttl_a, trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig_n : std_logic_vector(g_nr_ttl_chan downto 1);
signal ttlbar_nosig_n : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
......@@ -497,20 +515,18 @@ begin
-- error is detected from the bridge module.
p_i2c_err_led : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (i2c_err = '1') then
i2c_err_led <= '1';
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (i2c_err = '1') then
i2c_err_led <= '1';
end if;
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
......@@ -534,9 +550,16 @@ begin
--============================================================================
-- Converter board registers
--============================================================================
-- set unused wishbone outputs
xbar_master_in(c_slv_conv_regs).int <= '0';
xbar_master_in(c_slv_conv_regs).rty <= '0';
xbar_master_in(c_slv_conv_regs).err <= '0';
-- set SWITCH and RTM fields
switches_n <= ttl_switch_n_i & extra_switch_n_i(7 downto 1);
rtm_lines <= rtmp & rtmm;
-- and instantiate the component
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_n,
......@@ -693,19 +716,28 @@ begin
--============================================================================
inv_out_o <= inv_in_n_i;
-- cmp_tmp_pulse_gen : pulse_gen_gp
-- generic map
-- (
-- g_pwidth => 100,
-- g_freq => 125*(10**6)
-- )
-- port map
-- (
-- clk_i => clk125,
-- rst_n_i => rst_n,
-- pulse_o => tmp_pulse
-- );
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in(c_slv_multiboot).int <= '0';
xbar_master_in(c_slv_multiboot).rty <= '0';
xbar_master_in(c_slv_multiboot).err <= '0';
cmp_multiboot : xil_multiboot
port map
(
clk_i => clk125,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......
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