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Conv TTL Blocking - Gateware
Commit 4e7feccb authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Updated project files 

There was an issue with the pulsetest project file, in that it did
not have correct file references. The issue has now been fixed.
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 4e0ed399
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Showing with 132 additions and 436 deletions
syn/pulsetest/Makefile
View file @ 4e7feccb
......@@ -58,106 +58,23 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
......@@ -215,6 +132,10 @@ FILES := ../../top/pulsetest/pulsetest.ucf \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
......
syn/pulsetest/pulsetest.xise
View file @ 4e7feccb
......@@ -146,6 +146,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -302,6 +305,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
......@@ -402,526 +406,293 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
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<file xil_pn:name="../../modules/xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../modules/xil_multiboot/xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
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......
syn/regtest/regtest.xise
View file @ 4e7feccb
......@@ -146,6 +146,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -302,6 +305,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
......
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