Skip to content

C
Conv TTL Blocking - Gateware
Commit 4c0dd945 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

doc: Added pulse counters and other changes 

- folder structure updated
- getting around the code made clearer
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent f7b0232e
Hide whitespace changes
Inline Side-by-side
Showing with 845 additions and 340 deletions
doc/hdlguide/cern-title.tex
View file @ 4c0dd945
......@@ -9,9 +9,9 @@
\noindent \rule{\textwidth}{.1cm}
\hfill Gateware v1.0
\hfill Gateware v1.1
\hfill January 5, 2014
\hfill January 28, 2014
\vspace*{3cm}
......
doc/hdlguide/fig/arch.svg
View file @ 4c0dd945
......@@ -13,7 +13,7 @@
height="430.57178"
id="svg2"
version="1.1"
inkscape:version="0.48.4 r9939"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="arch.svg">
<defs
id="defs4">
......@@ -137,14 +137,14 @@
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="0.98994949"
inkscape:cx="-16.795407"
inkscape:cy="203.48188"
inkscape:zoom="1.979899"
inkscape:cx="114.59102"
inkscape:cy="261.43892"
inkscape:document-units="px"
inkscape:current-layer="layer1"
inkscape:current-layer="g3109"
showgrid="true"
inkscape:window-width="1535"
inkscape:window-height="876"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
......@@ -357,14 +357,14 @@
<text
sodipodi:linespacing="125%"
id="text4429-6"
y="309.29971"
y="314.58044"
x="389.97046"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
id="tspan4540"
y="309.29971"
y="314.58044"
x="389.97046"
sodipodi:role="line">CSR instantiation</tspan></text>
sodipodi:role="line"
id="tspan3051">Converter board registers</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutL)"
d="m 371.04188,339.82863 0,45.66929"
......@@ -375,17 +375,13 @@
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="389.97046"
y="361.4801"
y="367.73007"
id="text4435-2"
sodipodi:linespacing="125%"><tspan
id="tspan4542"
sodipodi:role="line"
x="389.97046"
y="361.4801">Pulse generation and pulse</tspan><tspan
id="tspan3068"
sodipodi:role="line"
x="389.97046"
y="373.9801">status logic</tspan></text>
y="367.73007">Channel logic</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
......
doc/hdlguide/fig/hdl-bd.svg
View file @ 4c0dd945
......@@ -10,10 +10,10 @@
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="524.57092"
height="346.47241"
height="409.48032"
id="svg2"
version="1.1"
inkscape:version="0.48.4 r9939"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="hdl-bd.svg"
inkscape:export-filename="/home/tstana/Desktop/hdl-bd.png"
inkscape:export-xdpi="72"
......@@ -196,14 +196,14 @@
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="0.98994949"
inkscape:cx="275.4181"
inkscape:cy="101.8227"
inkscape:zoom="1.4"
inkscape:cx="226.24362"
inkscape:cy="112.39196"
inkscape:document-units="px"
inkscape:current-layer="layer1"
inkscape:current-layer="g3974"
showgrid="true"
inkscape:window-width="1535"
inkscape:window-height="876"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
......@@ -227,7 +227,7 @@
spacingx="0.5mm"
spacingy="0.5mm"
originx="-15.346647mm"
originy="-122.21778mm" />
originy="-109.71778mm" />
</sodipodi:namedview>
<metadata
id="metadata7">
......@@ -245,25 +245,24 @@
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-54.377884,-272.83463)">
transform="translate(-54.377884,-254.11807)">
<g
id="g3974">
<rect
transform="translate(54.377884,272.83463)"
y="217.91336"
x="140.50401"
height="106.29921"
y="490.43231"
x="194.7872"
height="162.99213"
width="239.17322"
id="rect3118"
style="fill:#000000;fill-opacity:0.30000001;stroke:none" />
style="fill:#000000;fill-opacity:0.3;stroke:none" />
<path
sodipodi:nodetypes="ccccc"
inkscape:connector-curvature="0"
id="path12854"
d="m 377.36221,514.47406 0,21.25984 -138.18898,0 0,23.0315 15.94488,0"
d="m 377.36221,565.65744 0,21.25984 -138.18898,0 0,23.0315 15.94488,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<g
transform="translate(0,11.574489)"
transform="translate(0,62.757873)"
id="g9909">
<path
sodipodi:nodetypes="cccc"
......@@ -283,22 +282,22 @@
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path12624"
d="m 233.85827,514.47406 22.24515,0"
d="m 233.85827,565.65744 22.24515,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<path
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
id="path3936"
d="m 208.80512,505.61579 c 5.31496,7.08661 5.31496,10.62992 0,17.71654 12.04146,0 21.25984,0 26.5748,-8.85827 -5.31496,-8.85827 -14.53334,-8.85827 -26.5748,-8.85827 z"
d="m 208.80512,556.79917 c 5.31496,7.08661 5.31496,10.62992 0,17.71654 12.04146,0 21.25984,0 26.5748,-8.85827 -5.31496,-8.85827 -14.53334,-8.85827 -26.5748,-8.85827 z"
style="fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path13508"
d="m 345.97244,515.22407 65.55119,-0.5"
d="m 345.97244,566.40745 65.55119,-0.5"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" />
<path
transform="translate(301.54037,531.69057)"
transform="translate(301.54037,582.87395)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
......@@ -311,54 +310,54 @@
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path13673"
d="m 312.31102,453.54327 144.77559,0"
d="m 345.47244,453.54327 111.61417,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="158.08882"
y="505.87473"
y="557.05811"
id="text14802"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="158.08882"
y="505.87473"
y="557.05811"
id="tspan14806"
style="font-size:12px;font-weight:bold;text-align:end;text-anchor:end">TTL inputs</tspan></text>
<text
sodipodi:linespacing="125%"
id="text14810"
y="530.13928"
y="581.32269"
x="158.08882"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:12px;font-weight:bold;text-align:end;text-anchor:end"
id="tspan14812"
y="530.13928"
y="581.32269"
x="158.08882"
sodipodi:role="line">Blocking inputs</tspan></text>
<text
sodipodi:linespacing="125%"
id="text14814"
y="509.15912"
y="560.34253"
x="465.88629"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:12px;font-weight:bold;text-align:start;text-anchor:start"
id="tspan14816"
y="509.15912"
y="560.34253"
x="465.88629"
sodipodi:role="line">TTL outputs</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="464.84332"
y="528.64728"
y="579.83069"
id="text14818"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="464.84332"
y="528.64728"
y="579.83069"
id="tspan14820"
style="font-size:12px;font-weight:bold;text-align:start;text-anchor:start">Blocking outputs</tspan></text>
<text
......@@ -379,56 +378,56 @@
y="465.19281"
style="font-size:12px;font-weight:bold;text-align:start;text-anchor:start">supply reset</tspan></text>
<rect
y="273.83463"
x="177.16539"
height="344.47241"
width="265.74799"
y="255.11807"
x="177.16536"
height="407.48032"
width="265.74802"
id="rect4649"
style="opacity:0.5;fill:none;stroke:#323333;stroke-width:2;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:6, 6;stroke-dashoffset:0" />
<text
sodipodi:linespacing="125%"
id="text4651"
y="611.00165"
x="182.96681"
y="270.86472"
x="181.19516"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;opacity:0.5;fill:#333333;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:14px;font-weight:bold;fill:#333333;fill-opacity:1"
y="611.00165"
x="182.96681"
y="270.86472"
x="181.19516"
id="tspan4653"
sodipodi:role="line">FPGA</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3095"
y="590.90271"
y="642.08612"
x="158.08882"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:12px;font-weight:bold;text-align:end;text-anchor:end"
id="tspan3097"
y="590.90271"
y="642.08612"
x="158.08882"
sodipodi:role="line">INV-TTL inputs</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="464.84332"
y="591.21814"
y="642.40155"
id="text3099"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="464.84332"
y="591.21814"
y="642.40155"
id="tspan3101"
style="font-size:12px;font-weight:bold;text-align:start;text-anchor:start">INV-TTL outputs</tspan></text>
<path
inkscape:connector-curvature="0"
id="path3085"
d="m 411.52363,523.83234 0,-17.71654 44.29134,0"
d="m 411.52363,575.01572 0,-17.71654 44.29134,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#marker3114)"
d="m 411.52363,506.1158 0,17.71654 44.29134,0"
d="m 411.52363,557.29918 0,17.71654 44.29134,0"
id="path3087"
inkscape:connector-curvature="0" />
<g
......@@ -714,7 +713,7 @@
d="m 165.26378,423.43679 22.5315,-0.0116"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:square;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#marker3114)" />
<g
transform="translate(0,28.346538)"
transform="translate(33.661414,28.346538)"
id="g4081">
<rect
y="418.11017"
......@@ -742,12 +741,6 @@
id="path4073"
d="m 210.82678,423.42516 17.71653,0 0,-24.80315 12.40158,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path4075"
d="m 278.14961,443.41335 0,-40.74803"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#marker3106)" />
<path
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
......@@ -767,7 +760,7 @@
d="m 313.58268,308.26768 26.5748,0"
style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:url(#TriangleInS);marker-end:url(#TriangleOutS)" />
<g
transform="translate(-80.996053,383.87174)"
transform="translate(-80.996053,435.05512)"
id="g9631">
<rect
style="opacity:0.98999999;fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
......@@ -792,12 +785,12 @@
<path
sodipodi:nodetypes="ccc"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#marker3114);marker-mid:url(#marker3114);marker-end:url(#marker3114)"
d="m 164.76378,587.59218 145.40875,0.25023 145.14243,0.24977"
d="m 164.76378,638.77556 145.40875,0.25023 145.14243,0.24977"
id="path10174"
inkscape:connector-curvature="0" />
<g
id="g10992"
transform="translate(-80.996053,427.16307)">
transform="translate(-80.996053,478.34645)">
<rect
y="122.24406"
x="340.15747"
......@@ -820,7 +813,7 @@
</g>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 345.97244,558.5154 65.55119,-0.5"
d="m 345.97244,609.69878 65.55119,-0.5"
id="path11000"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
......@@ -833,40 +826,40 @@
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="translate(301.54037,574.9819)" />
transform="translate(301.54037,626.16528)" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="465.88629"
y="553.34021"
y="604.52362"
id="text11004"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="465.88629"
y="553.34021"
y="604.52362"
id="tspan11006"
style="font-size:12px;font-weight:bold;text-align:start;text-anchor:start">TTL LEDs</tspan></text>
<text
sodipodi:linespacing="125%"
id="text11008"
y="571.42584"
y="622.60925"
x="464.84332"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:12px;font-weight:bold;text-align:start;text-anchor:start"
id="tspan11010"
y="571.42584"
y="622.60925"
x="464.84332"
sodipodi:role="line">Blocking LEDs</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#marker3114)"
d="m 411.52363,567.12367 0,-17.71654 44.29134,0"
d="m 411.52363,618.30705 0,-17.71654 44.29134,0"
id="path11012"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path11014"
d="m 411.52363,549.40713 0,17.71654 44.29134,0"
d="m 411.52363,600.59051 0,17.71654 44.29134,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<path
sodipodi:type="arc"
......@@ -877,54 +870,58 @@
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="translate(267.37897,531.69057)" />
<path
sodipodi:nodetypes="cc"
transform="translate(61.422577,68.094452)"
inkscape:connector-curvature="0"
id="path14092"
d="m 266.33333,385.44882 0,-30.11811"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)"
d="m 327.75591,454.04327 0,30.11811"
id="path14518"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
transform="translate(217.77267,470.50977)"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
sodipodi:ry="1.7716535"
sodipodi:rx="1.7716535"
sodipodi:cy="-16.716501"
sodipodi:cx="109.98324"
id="path14524"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
sodipodi:type="arc" />
<path
transform="translate(54.377884,272.83463)"
inkscape:connector-curvature="0"
id="path4170"
d="m 273.37802,166.53541 10.62992,-10.62992"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)" />
<path
transform="translate(54.377884,272.83463)"
inkscape:connector-curvature="0"
id="path4376"
d="M 273.34822,166.47241 262.7481,155.8723"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)" />
<path
transform="translate(54.377884,272.83463)"
inkscape:connector-curvature="0"
id="path4582"
d="m 273.37802,196.65352 -8.85827,8.85827"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)" />
<path
transform="translate(54.377884,272.83463)"
inkscape:connector-curvature="0"
id="path4788"
d="m 273.37802,196.65352 8.85827,8.85827"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)" />
transform="translate(267.37897,582.87395)" />
<g
id="g3172"
transform="translate(53.149609,0)">
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)"
d="m 266.33333,385.44882 0,-30.11811"
id="path14092"
inkscape:connector-curvature="0"
transform="translate(61.422577,68.094452)"
sodipodi:nodetypes="cc" />
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path14518"
d="m 327.75591,454.04327 0,30.11811"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<path
sodipodi:type="arc"
style="fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="path14524"
sodipodi:cx="109.98324"
sodipodi:cy="-16.716501"
sodipodi:rx="1.7716535"
sodipodi:ry="1.7716535"
d="m 111.75489,-16.716501 c 0,0.978457 -0.79319,1.771653 -1.77165,1.771653 -0.97846,0 -1.77166,-0.793196 -1.77166,-1.771653 0,-0.978457 0.7932,-1.771654 1.77166,-1.771654 0.97846,0 1.77165,0.793197 1.77165,1.771654 z"
transform="translate(217.77267,470.50977)" />
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)"
d="m 273.37802,166.53541 10.62992,-10.62992"
id="path4170"
inkscape:connector-curvature="0"
transform="translate(54.377884,272.83463)" />
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)"
d="M 273.34822,166.47241 262.7481,155.8723"
id="path4376"
inkscape:connector-curvature="0"
transform="translate(54.377884,272.83463)" />
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)"
d="m 273.37802,196.65352 -8.85827,8.85827"
id="path4582"
inkscape:connector-curvature="0"
transform="translate(54.377884,272.83463)" />
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:2, 2;stroke-dashoffset:0;marker-end:url(#marker3114)"
d="m 273.37802,196.65352 8.85827,8.85827"
id="path4788"
inkscape:connector-curvature="0"
transform="translate(54.377884,272.83463)" />
</g>
<text
sodipodi:linespacing="125%"
id="text3960"
......@@ -937,6 +934,77 @@
y="500.01038"
x="196.65355"
sodipodi:role="line">channel logic x6</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)"
d="m 377.36221,565.15744 0,21.25984 -138.18898,0 0,23.0315 15.94488,0"
id="path3152"
inkscape:connector-curvature="0"
sodipodi:nodetypes="ccccc" />
<g
transform="translate(-80.996053,478.34645)"
id="g3154">
<rect
style="opacity:0.98999999;fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect3156"
width="86.811035"
height="17.716537"
x="340.15747"
y="122.24406" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="351.05811"
y="133.72195"
id="text3158"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
x="351.05811"
y="133.72195"
style="font-weight:bold;text-align:start;text-anchor:start"
id="tspan3160">p_pulse_led</tspan></text>
</g>
<path
sodipodi:nodetypes="ccccc"
inkscape:connector-curvature="0"
id="path3162"
d="m 377.36221,566.9291 0,-21.25984 -138.18898,0 0,-23.0315 15.94488,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)" />
<g
id="g3164"
transform="translate(-80.996053,390.26378)">
<rect
y="122.24406"
x="340.15747"
height="17.716537"
width="86.811035"
id="rect3166"
style="opacity:0.98999999;fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
<text
sodipodi:linespacing="125%"
id="text3168"
y="133.72195"
x="351.05811"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
id="tspan3170"
style="font-weight:bold;text-align:start;text-anchor:start"
y="133.72195"
x="351.05811"
sodipodi:role="line">p_pulse_cnt</tspan></text>
</g>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#marker3106);marker-end:url(#marker3114)"
d="m 204.28353,132.87399 0,70.86615 44.29134,0 0,31.88976"
id="path4635"
inkscape:connector-curvature="0"
transform="translate(54.377884,272.83463)"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#marker3114)"
d="m 243.25991,129.33069 0,40.74803"
id="path5045"
inkscape:connector-curvature="0"
transform="translate(54.377884,272.83463)" />
</g>
</g>
</svg>
doc/hdlguide/fig/pulse-cnt.svg 0 → 100644
View file @ 4c0dd945
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="371.96677"
height="94.647644"
id="svg3259"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="pulse-cnt.svg">
<defs
id="defs3261" />
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="2.8"
inkscape:cx="163.73485"
inkscape:cy="-22.945261"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
showguides="true"
inkscape:guide-bbox="true"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1">
<inkscape:grid
type="xygrid"
id="grid71895"
empspacing="5"
visible="true"
enabled="true"
snapvisiblegridlinesonly="true"
units="mm"
spacingx="0.5mm"
spacingy="0.5mm"
originx="-30.163826mm"
originy="-190.85889mm" />
</sodipodi:namedview>
<metadata
id="metadata3264">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title />
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-106.8797,-281.44291)">
<g
transform="translate(49.606305,12.401572)"
id="g6859">
<rect
y="311.811"
x="212.59842"
height="40.748032"
width="35.433071"
id="rect6649"
style="fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
inkscape:connector-curvature="0"
id="path6651"
d="m 225,341.92911 -5.31496,0 10.62992,0 0,-19.48819 10.62992,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" />
<path
sodipodi:nodetypes="ccc"
inkscape:connector-curvature="0"
id="path6653"
d="m 226.77165,333.07084 3.54331,-3.5433 3.54331,3.5433"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" />
</g>
<g
id="g72719"
transform="translate(58.46457,12.401572)">
<rect
style="fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect6857"
width="35.433071"
height="40.748032"
x="290.55118"
y="311.811" />
<text
sodipodi:linespacing="125%"
id="text6864"
y="339.47507"
x="292.55969"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:20px;font-weight:bold"
y="339.47507"
x="292.55969"
id="tspan6866"
sodipodi:role="line">+1</tspan></text>
</g>
<path
sodipodi:nodetypes="cc"
inkscape:connector-curvature="0"
id="path71899"
d="m 297.6378,334.8425 51.37795,0"
style="fill:#000000;fill-opacity:0;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" />
<g
id="g3838"
transform="translate(-17.71654,0)">
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#808080;fill-opacity:1;stroke:none;font-family:Sans"
x="148.81889"
y="324.21259"
id="text72715"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan72717"
x="148.81889"
y="324.21259"
style="font-size:12px;font-weight:bold;text-align:end;text-anchor:end;fill:#808080;fill-opacity:1">TTL</tspan></text>
<text
sodipodi:linespacing="125%"
id="text72724"
y="373.81888"
x="148.81889"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#808080;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:12px;font-weight:bold;text-align:end;text-anchor:end;fill:#808080;fill-opacity:1"
y="373.81888"
x="148.81889"
id="tspan72726"
sodipodi:role="line">Blo</tspan></text>
<g
id="g3825">
<path
style="fill:none;stroke:#808080;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 189.56693,341.92911 -21.25984,0 0,-21.25984 -17.71654,0"
id="path72681"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
<path
sodipodi:nodetypes="cccc"
inkscape:connector-curvature="0"
id="path72683"
d="m 189.56693,349.01573 -21.25984,0 0,21.25984 -17.71654,0"
style="fill:none;stroke:#808080;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" />
<path
style="fill:#ffffff;fill-opacity:1;stroke:#808080;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 185.02362,336.87137 c 5.16063,6.88084 5.16063,10.32125 0,17.20209 12.04146,0 20.64251,0 25.80315,-8.60104 -5.16064,-8.60105 -13.76169,-8.60105 -25.80315,-8.60105 z"
id="path3936"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccc" />
</g>
</g>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 460.62992,310.03937 17.71653,0 0,65.55118 -150.59054,0 0,-21.25985 21.25984,0"
id="path72701"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cccccc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="133.92857"
y="317.36218"
id="text72703"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan72705"
x="133.92857"
y="317.36218" /></text>
<g
id="g3789"
transform="translate(37.110285,26.574805)">
<rect
style="fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3008"
width="77.952759"
height="22.778404"
x="269.38577"
y="257.0163" />
<text
sodipodi:linespacing="125%"
id="text3010"
y="270.35083"
x="274.60629"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:12px;font-weight:bold"
y="270.35083"
x="274.60629"
id="tspan3012"
sodipodi:role="line">conv_regs</tspan></text>
</g>
<g
id="g4443"
transform="translate(0,8.8582839)">
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 446.45669,334.84252 5.31496,-8.85827 5.31496,8.85827"
id="path3794"
inkscape:connector-curvature="0" />
<rect
y="272.83463"
x="442.91339"
height="62.007889"
width="17.71653"
id="rect3019"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
</g>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 292.44242,28.236252 30.11812,0 0,-17.716534 28.34645,0"
id="path3796"
inkscape:connector-curvature="0"
transform="translate(92.006394,315.46453)"
sodipodi:nodetypes="cccc" />
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 384.44881,290.55118 58.46457,0"
id="path3798"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 384.44881,301.1811 58.46457,0"
id="path3800"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
<text
xml:space="preserve"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="439.37009"
y="288.77951"
id="text3813"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3815"
x="439.37009"
y="288.77951"
style="font-size:8px;text-align:end;text-anchor:end">load</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3821"
y="299.40945"
x="439.37009"
style="font-size:40px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:8px;text-align:end;text-anchor:end"
y="299.40945"
x="439.37009"
id="tspan3823"
sodipodi:role="line">val</tspan></text>
<g
id="g6894"
transform="translate(72.637785,-76.18111)">
<rect
y="414.56689"
x="132.87401"
height="26.574816"
width="17.716543"
id="rect6886"
style="fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<path
inkscape:connector-curvature="0"
id="path6888"
d="m 132.87402,434.0551 3.5433,1.77165 -3.5433,1.77165"
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
</g>
<g
id="g6898"
transform="translate(72.637785,-76.18111)">
<rect
style="fill:#cccccc;fill-opacity:1;stroke:#000000;stroke-width:0.5;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect6890"
width="17.716543"
height="26.574816"
x="159.44882"
y="414.56689" />
<path
style="fill:none;stroke:#000000;stroke-width:0.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
d="m 159.44883,434.0551 3.5433,1.77165 -3.5433,1.77165"
id="path6892"
inkscape:connector-curvature="0" />
</g>
<path
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 223.22834,345.47243 8.85827,0"
id="path7100"
inkscape:connector-curvature="0" />
<path
inkscape:connector-curvature="0"
id="path4439"
d="m 193.11023,345.47243 12.40158,0"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
sodipodi:nodetypes="cc" />
<path
sodipodi:nodetypes="cc"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
d="m 249.80314,345.47243 12.40158,0"
id="path4441"
inkscape:connector-curvature="0" />
</g>
</svg>
doc/hdlguide/hdlguide-conv-ttl-blo.bib
View file @ 4c0dd945
......@@ -62,3 +62,8 @@
note = {v2.5},
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{wbgen2,
title = {{Wishbone Slave Generator}},
howpublished = {\url{http://www.ohwr.org/projects/wishbone-gen/wiki}}
}
doc/hdlguide/hdlguide-conv-ttl-blo.tex
View file @ 4c0dd945
......@@ -17,8 +17,12 @@
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{longtable}
\usepackage[toc,page]{appendix}
\usepackage{pbox}
% Header and footer customization
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
......@@ -53,9 +57,10 @@
26-07-2013 & 0.2 & Second draft \\
07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\
29-10-2013 & 1.03 & Added MultiBoot support to firmware \\
29-10-2013 & 1.03 & Added MultiBoot support to gateware \\
20-11-2013 & 1.04 & Changed system clock to 20~MHz \\
05-01-2014 & 1.05 & Updated folder structure and renamed \textit{vbcp\_wb} to \textit{i2c\_bridge} \\
28-01-2014 & 1.06 & Added pulse counters in HDL \\
\hline
\end{tabular}
}
......@@ -79,6 +84,7 @@ FSM & Finite-State Machine \\
IC & Integrated Circuit \\
I$^2$C & Inter-Integrated Circuit (bus) \\
PLL & Phase-Locked Loop \\
RTM & Rear-Transition Module \\
SPI & Serial Peripheral Interface \\
SysMon & (ELMA) System Montior \\
VCXO & Voltage-controlled oscillator \\
......@@ -99,17 +105,23 @@ board. The HDL (mostly implemented in VHDL) handles the following aspects of
the CONV-TTL-BLO capabilities:
\begin{itemize}
\item pulse detection (on pulse rising edge)
\item fixed-width pulse generation
\item status retrieval via I$^2$C
\item fixed-width pulse generation with pulse rejection
\item status retrieval (diagnostics) via I$^2$C
\begin{itemize}
\item gateware version
\item switches and RTM detection lines
\item pulse counters
\item remote reset
\end{itemize}
\item remote reprogramming via I$^2$C
\end{itemize}
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL firmware. Each of the
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL gateware. Each of the
blocks in the figure is presented in following sections.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/hdl-bd}}
\caption{Block diagram of FPGA firmware}
\caption{Block diagram of FPGA gateware}
\label{fig:hdl-bd}
\end{figure}
......@@ -123,177 +135,6 @@ blocks in the figure is presented in following sections.
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\end{itemize}
%======================================================================================
% SEC: Folder structure
%======================================================================================
\section{Folder Structure}
\label{sec:fold-struct}
The folder structure for the project is presented below.
\renewcommand{\labelitemi}{$\rightarrow$}
\renewcommand{\labelitemii}{$\rightarrow$}
\renewcommand{\labelitemiii}{$\rightarrow$}
\renewcommand{\labelitemiv}{$\rightarrow$}
\begin{itemize}
\item conv-ttl-blo-gw/
\begin{itemize}
\item doc/
\begin{itemize}
\item hdlguide/
\end{itemize}
\item ip\_cores/
\begin{itemize}
\item general-cores/
\end{itemize}
\item modules/
\begin{itemize}
\item Release/
% \begin{itemize}
% \item conv\_regs.vhd
% \item conv\_regs.wb
% \end{itemize}
\item pulsetest/
% \begin{itemize}
% \item conv\_regs.vhd
% \item conv\_regs.wb
% \item pgen\_ctrl\_regs.vhd
% \item pgen\_ctrl\_regs.wb
% \item pulse\_cnt\_regs.vhd
% \item pulse\_cnt\_regs.wb
% \item pulse\_gen\_gp.vhd
% \end{itemize}
\item ctb\_pulse\_gen.vhd
\item reset\_gen.vhd
\item rtm\_detector.vhd
\end{itemize}
\item sim/
\item syn/
\begin{itemize}
\item Release/
\item pulsetest/
\item regtest/
\end{itemize}
\item top/
\begin{itemize}
\item Release/
\begin{itemize}
\item conv\_ttl\_blo.ucf
\item conv\_ttl\_blo.vhd
\end{itemize}
\item pulsetest/
\begin{itemize}
\item pulsetest.ucf
\item pulsetest.vhd
\end{itemize}
\item regtest/
\begin{itemize}
\item pulsetest.ucf
\item pulsetest.vhd
\end{itemize}
\end{itemize}
\end{itemize}
\end{itemize}
Gateware files are organized on a per type-of-project basis. There are two different types of
projects for CONV-TTL-BLO gateware: the \textit{release project} and \textit{test projects}.
The release project is the latest production firmware version, that goes on the CONV-TTL-BLO
board used in the field. Test projects are meant to be downloaded to a CONV-TTL-BLO for
testing the CONV-TTL-BLO system under long-term test conditions. The projects present in the
repository at the time of writing of this document are presented in Table~\ref{tbl:fold-struct-proj}.
\begin{table}[h]
\caption{Gateware projects in the repository}
\label{tbl:fold-struct-proj}
\centerline
{
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Project}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{conv\_ttl\_blo} & Design-wide release project to be used in the field \\
\textit{regtest} & Long-term test for testing the I$^2$C communication by writing
to a RAM on the FPGA \\
\textit{pulsetest} & Long-term test for testing pulse repetition on the CONV-TTL-BLO \\
\hline
\end{tabular}
}
\end{table}
As can be seen from the folder structure above, gateware files are organized in the
\textit{modules/}, \textit{syn/} and \textit{top/} folders following this project convention.
Files in these folders (where relevant) are organized in the \textit{Release/}, \textit{pulsetest/}
and \textit{regtest/} folders, where the \textit{Release/} folder of course represents the
release firmware and the other two are test projects, as their names suggest.
HDL files are organized into modules and top-level files. Modules are blocks used within the
design, while top-level files combine modules together into a design. Modules relevant for the
whole design are stored directly under the \textit{modules/} folder, while modules specific
to a certain project are stored within the project's sub-folder in the \textit{modules/} folder.
Apart from the top folder of the design, the \textit{top/} folder for each project also contains
the .ucf constraints file for synthesis.
One place where the project structure is not necessarily enforced is the \textit{sim/} folder.
This folder is meant to contain files relevant for simulation of various modules within
the design and as such can be composed of folders named after the component to be simulated.
The \textit{syn/} folder holds the actual project files for Xilinx ISE, as well as other
various output files from ISE. Each ISE project, be it for release or test project, together
with its output files, is contained within its own sub-folder in the \textit{syn/} folder.
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\section{Getting Around the Code}
\label{sec:get-around}
Code in the top-level files is organized in code sections. A code section is a piece of code
pertaining to a certain part of the design, where component instantiations and input and
output port assignments are made. For example, there is a section pertaining to
pulse repetition, where there is a generate block to generate the logic necessary for pulse
repetition on each channel, including the pulse status LEDs.
\begin{figure}[h]
\centerline{\includegraphics[width=.59\textwidth]{fig/arch}}
\caption{VHDL architecture of the release firmware}
\label{fig:arch}
\end{figure}
Ports and signals usually follow the coding guideline at~\cite{coding-guidelines}. Most of the
top-level ports of the firmware are lower-case versions of their schematics counterparts. The
exceptions from this are due to either net names that could not be syntactically represented in
VHDL, or net names that have been made clearer in VHDL code.
The declarative part of the architecture is organized as shown in Figure~\ref{fig:arch}~(a).
Types are declared right after the architecture declaration, followed by constant
declarations, followed by component declarations, after which the various signals
are declared.
The body of the architecture is organised in code sections as shown in
Figure~\ref{fig:arch}~(b). It starts with the instantiation of the \textit{reset\_gen}
component which generates the board-wide reset.
Then, in the I$^2$C section, the I$^2$C bridge component is instantiated,
the logic for lighting the I2C front panel LED is defined, as well as the CWDTO bit
in the SR (see Appendix~\ref{app:memmap-csr}). Before the end of this section, an
\textit{xwb\_crossbar} is instantiated to communicate to the various peripherals.
The I$^2$C section is followed by the main code section of the design, the pulse
generation section. Here, a generate block is used to generate the logic for each
channel, including the instantiation of a \textit{ctb\_pulse\_gen} block, the
implementation of the no signal detect block (see Section~\ref{sec:pulse-gen-brdlvl}),
the output pulse assignments and the logic for flashing the pulse LED for 262~ms.
After the pulse generation section, the MultiBoot component is instantiated and
connected to the SPI pins to and from the on-board flash chip.
Two more short code sections remain, that in which the \textit{bicolor\_led\_ctrl}
component is connected to the line and column outputs to the bicolor LED matrix,
and the connection of the RTM detection inputs to the \textit{rtm\_detector}
component.
%==============================================================================
% SEC: Clocks
%==============================================================================
......@@ -307,7 +148,7 @@ of 125~MHz is generated on-board via a Texas Instruments PLL IC from a 25~MHz VC
Two DACs are provided on-board for controlling the two VCXOs. The DACs can be
controlled via SPI, but this feature is not yet implemented.
Table~\ref{tbl:clocks} lists the clock domains used in the firmware.
Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/clocks}}
......@@ -368,8 +209,8 @@ signal is de-asserted, the counter is disabled and the \textit{reset\_gen}
module remains inactive.
The module reactivates on the power-on reset, or when a reset is triggered externally, via
the \textit{rst\_i} pin. The \textit{rst\_i} pin is tied in the design to the first bit
in the control register (CR, see Appendix~\ref{app:memmap-csr}), which has to be first
the \textit{rst\_i} pin. The \textit{rst\_i} pin is tied in the design to the second bit
in the control register (CR -- see Appendix~\ref{app:memmap-cr}), which has to be first
unlocked by writing the RST\_UNLOCK bit. Both these registers are implemented in the
top-level file of the design.
......@@ -413,12 +254,12 @@ module sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the
The \textit{rtmm\_ok} and \textit{rtmp\_ok} signals are NANDed together to light
the ERR status LED on the CONV-TTL-BLO. The status of the RTM detection lines
can also be read via their respective fields in the CONV board status register
(see Appendix~\ref{app:memmap-csr}).
can also be read via their respective fields in the converter board status register
(SR -- see Appendix~\ref{app:memmap-sr}).
\begin{figure}[h]
\centerline{\includegraphics[width=.85\textwidth]{fig/rtm-detect}}
\caption{\textit{rtm\_detector} block in CONV-TTL-BLO firmware}
\centerline{\includegraphics[width=.76\textwidth]{fig/rtm-detect}}
\caption{\textit{rtm\_detector} block in CONV-TTL-BLO gateware}
\label{fig:rtm-detect}
\end{figure}
......@@ -509,10 +350,10 @@ line-second basis.
There are twelve bicolor LEDs on the CONV-TTL-BLO; they are connected in a two-line,
six-column pattern controlled by a \textit{bicolor\_led\_ctrl} block.
Table~\ref{tbl:bicolor-led-state-conn} shows the \textit{led\_state\_i} connections
for the bicolor status LEDs in the CONV-TTL-BLO firmware.
for the bicolor status LEDs in the CONV-TTL-BLO gateware.
\begin{table}[h]
\caption{LED state vector connections in the firmware}
\caption{LED state vector connections in the gateware}
\label{tbl:bicolor-led-state-conn}
\centerline
{
......@@ -676,6 +517,34 @@ channel.
\label{fig:no-sig-detect}
\end{figure}
%==============================================================================
% SEC: Pulse counters
%==============================================================================
\pagebreak
\section{Pulse counters}
\label{sec:pulse-cnt}
There are a total of six pulse counters implemented in the logic. Their
implementation is achieved via a single process -- \textit{p\_pulse\_cnt}.
Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
When a pulse arrives on either the TTL or blocking side, it is resynchronized
in the 20~MHz clock domain and passed through a rising edge detector. When
a rising edge occurs on the pulse, the counter is incremented by one and stored
to the channel pulse counter register (CHxPCR -- see Appendix~\ref{app:memmap-chpcr})
register.
Note that this register is implemented outside of the \textit{conv\_regs} component,
since it is a read-write register. When the register is written by the \textit{conv\_regs}
component, the \textit{load} output is asserted and the register is loaded with
the value received via I$^2$C.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
\caption{Pulse counter implementation}
\label{fig:pulse-cnt}
\end{figure}
%==============================================================================
% SEC: Mem-mapped periphs
%==============================================================================
......@@ -689,7 +558,7 @@ access these peripherals. The protocol, as well as the bridge component
translating I$^2$C accesses into Wishbone accesses, are defined in the bridge
component's documentation.
The complete memory map of the firmware can be found in Appendix~\ref{app:memmap}.
The complete memory map of the gateware can be found in Appendix~{app:memmap}.
%------------------------------------------------------------------------------
% SUBSEC: Statregs
......@@ -707,15 +576,23 @@ Details about the module's implementation can be found in its documentation.
%------------------------------------------------------------------------------
% SUBSEC: CSR
%------------------------------------------------------------------------------
\subsection{Control and status registers}
\label{sec:periphs-csr}
\subsection{Converter board registers}
\label{sec:periphs-conv-regs}
The status registers implemented in the firmware contain the current firmware
version, the position of the on-board switches and the values on RTM detection lines.
A set of registers are implemented as general-purpose registers for converter boards.
These are status and control registers implemented utilizing \textit{wbgen2}~\cite{wbgen2}.
Appendix~\ref{app:memmap-conv-regs} presents the converter board registers.
No control registers are currently implemented.
On the status registers side, there is one general status register (SR -- see
Appendix~\ref{app:memmap-sr}) that contains details about the gateware version,
the state of the on-board switches and RTM detection lines, as well as the state
of the communication watchdog timer. Then, there are six pulse counter registers
(CHxPCR -- see Appendix~\ref{app:memmap-chpcr}), one per each channel, which are updated
with the current values of the input pulse counters.
The logic also contains one control register (CR -- see Appendix~\ref{app:memmap-cr}),
which contains two bits for remotely resetting the FPGA logic.
See Appendix~\ref{app:memmap-csr} for more information.
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
......@@ -727,9 +604,220 @@ The MultiBoot module offers the remote reprogramming capabilities for the
CONV-TTL-BLO board. It offers a set of registers for controlling writing a bitstream
to the M25P32 flash chip and for issuing the remote reprogramming command.
For information on the module, refer to the module's documentation. The memory
map of the module is also present in this manual, for quick reference
(see Appendix~\ref{app:memmap-multiboot}).
For information on the module, refer to its documentation. The memory map of the
module is also present in this manual, for quick reference (see
Appendix~\ref{app:memmap-multiboot}).
%======================================================================================
% SEC: Folder structure
%======================================================================================
\section{Folder Structure}
\label{sec:fold-struct}
Gateware files are organized on a per type-of-project basis. There are two different types of
projects for CONV-TTL-BLO gateware: the \textit{release project} and \textit{test projects}.
The release project is the latest production gateware version, that goes on the CONV-TTL-BLO
board used in the field. Test projects are meant to be downloaded to a CONV-TTL-BLO for
testing the CONV-TTL-BLO system under long-term test conditions. The projects present in the
repository at the time of writing of this document are presented in Table~\ref{tbl:fold-struct-proj}.
\begin{table}[h]
\caption{Gateware projects in the repository}
\label{tbl:fold-struct-proj}
\centerline
{
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Project}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{conv\_ttl\_blo} & Design-wide release project to be used in the field \\
\textit{regtest} & Long-term test for testing the I$^2$C communication by writing
to a RAM on the FPGA \\
\textit{pulsetest} & Long-term test for testing pulse repetition on the CONV-TTL-BLO \\
\hline
\end{tabular}
}
\end{table}
The folder structure for the project is presented below.
\let \oldlabelitemi=\labelitemi
\let \oldlabelitemii=\labelitemii
\let \oldlabelitemiii=\labelitemiii
\let \oldlabelitemiv=\labelitemiv
\renewcommand{\labelitemi}{$\rightarrow$}
\renewcommand{\labelitemii}{$\rightarrow$}
\renewcommand{\labelitemiii}{$\rightarrow$}
\renewcommand{\labelitemiv}{$\rightarrow$}
\begin{itemize}
\item conv-ttl-blo-gw/
\begin{itemize}
\item doc/
\begin{itemize}
\item hdlguide/
\end{itemize}
\item ip\_cores/
\begin{itemize}
\item general-cores/
\end{itemize}
\item modules/
\begin{itemize}
\item Release/
\begin{itemize}
\item conv\_regs.vhd
\item conv\_regs.wb
\end{itemize}
\item pulsetest/
\begin{itemize}
\item pulse\_gen\_gp.vhd
\item {[}...{]}
\end{itemize}
\item ctb\_pulse\_gen.vhd
\item reset\_gen.vhd
\item rtm\_detector.vhd
\end{itemize}
\item sim/
\item syn/
\begin{itemize}
\item Release/
\item pulsetest/
\item regtest/
\end{itemize}
\item top/
\begin{itemize}
\item Release/
\begin{itemize}
\item conv\_ttl\_blo.ucf
\item conv\_ttl\_blo.vhd
\end{itemize}
\item pulsetest/
% \begin{itemize}
% \item pulsetest.ucf
% \item pulsetest.vhd
% \end{itemize}
\item regtest/
% \begin{itemize}
% \item pulsetest.ucf
% \item pulsetest.vhd
% \end{itemize}
\end{itemize}
\end{itemize}
\end{itemize}
\renewcommand{\labelitemi}{\oldlabelitemi}
\renewcommand{\labelitemii}{\oldlabelitemii}
\renewcommand{\labelitemiii}{\oldlabelitemiii}
\renewcommand{\labelitemiv}{\oldlabelitemiv}
\begin{table}[h]
\caption{Folder structure}
\label{tbl:fold-struct}
\centerline
{
\begin{tabular}{l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Folder}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
doc/ & Documentation files \\
ip\_cores/ & IP cores used in the design \\
modules/ & Project-specific modules instantiated in the top-level design \newline
Organized on a project type basis \\
sim/ & Module simulation files \\
syn/ & ISE project file and synthesis output files, including binaries to
download to the FPGA \newline
Organized on a project type basis \\
top/ & Top-level .vhd and .ucf files \newline
Organized on a project type basis \\
\hline
\end{tabular}
}
\end{table}
As can be seen from the folder structure above, gateware files are organized in the
\textit{modules/}, \textit{syn/} and \textit{top/} folders following this project convention.
Files in these folders (where relevant) are organized in the \textit{Release/}, \textit{pulsetest/}
and \textit{regtest/} folders, where the \textit{Release/} folder of course represents the
release gateware and the other two are test projects, as their names suggest.
One place where the project structure is not necessarily enforced is the \textit{sim/} folder.
This folder is meant to contain files relevant for simulation of various modules within
the design and as such can be composed of folders named after the component to be simulated.
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\section{Getting Around the Code}
\label{sec:get-around}
Ports and signals usually follow the coding guideline at~\cite{coding-guidelines}. Most of the
top-level ports of the gateware are lower-case versions of their schematics counterparts. The
exceptions from this are due to either net names that could not be syntactically represented in
VHDL, or net names that have been made clearer in VHDL code.
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth]{fig/arch}}
\caption{VHDL architecture of the release gateware}
\label{fig:arch}
\end{figure}
Code in the top-level files is organized in code sections. A code section is a piece of code
pertaining to a certain part of the design, where component instantiations and input and
output port assignments are made. For example, there is a section pertaining to
pulse repetition, where there is a generate block to generate the logic necessary for pulse
repetition on each channel, including the pulse status LEDs.
The VHDL architecture of the top-level file of the release gateware is shown
in Figure~\ref{fig:arch}. Table~\ref{tbl:arch} lists the code sections of the
top-level file.
\begin{longtable}{p{.25\textwidth} p{.65\textwidth}}
\caption{Code sections in the FPGA gateware}
\label{tbl:arch} \\
% FIRST HEADER %
\hline
\multicolumn{1}{c}{\textbf{Code section}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\endfirsthead
% OTHER HEADERS %
\hline
\multicolumn{1}{c}{\textbf{Code section}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\endhead
% FOOTERS %
\hline
\endfoot
% TABLE CONTENTS %
Reset logic & -- \textit{reset\_gen} instantiation \\
I$^2$C bridge & -- \textit{wb\_i2c\_bridge} instantiation \newline
-- logic for blinking the I2C bicolor LED on the front panel \newline
-- generate the CWDTO bit register \\
Converter boards
registers & -- \textit{conv\_regs} instantiation \newline
-- connect the switch lines to the SR \newline
-- connect the RTM detection lines to the SR \newline
-- generate the RST and RST\_UNLOCK bits registers \\
Channel logic & -- connect inputs to internal signals \newline \newline
A single VHDL \textit{generate} statement then generates the
channel logic: \newline
-- synchronization flip-flops on the input signals \newline
-- input pulse counter logic \newline
-- no signal detect block (Figure~\ref{fig:no-sig-detect}) \newline
-- \textit{ctb\_pulse\_gen} instantiation \newline
-- pulse output connections \newline
-- process to light pulse LEDs on pulse output \\
MultiBoot logic & -- \textit{wb\_xil\_multiboot} instantiation \\
Status LEDs & -- \textit{bicolor\_led\_ctrl} instantiation \newline
-- connecting the \textit{led\_state\_i} input of the
component to the relevant control signals \\
RTM detection & -- inverting the input signals from the RTM detection lines \newline
-- \textit{rtm\_detector} component instantiation \\
\end{longtable}
%==============================================================================
% Appendices
......@@ -743,9 +831,16 @@ map of the module is also present in this manual, for quick reference
\section{Memory map}
\label{app:memmap}
Table~\ref{tbl:memmap} shows the complete memory map of the firmware. The
Table~\ref{tbl:memmap} shows the complete memory map of the gateware. The
following sections list the memory map of each peripheral.
In order to convert address values to register index values for SNMP access,
the following formula should be used:
\begin{center}
$reg. index = \frac{addr}{4} + 1$
\end{center}
\begin{table}[h]
\caption{CONV-TTL-BLO memory map}
\label{tbl:memmap}
......@@ -756,32 +851,39 @@ following sections list the memory map of each peripheral.
\multicolumn{1}{c}{\textbf{Periph.}} & \multicolumn{2}{c}{\textbf{Address}} & \multicolumn{1}{c}{\textbf{Description}} \\
& \multicolumn{1}{c}{\textbf{Base}} & \multicolumn{1}{c}{\textbf{End}} & \\
\hline
CSR & 0x000 & 0x00f & Control and status register \\
MultiBoot & 0x040 & 0x05f & MultiBoot module \\
Board regs & 0x000 & 0x020 & Coverter board registers \\
MultiBoot & 0x040 & 0x050 & MultiBoot module \\
\hline
\end{tabular}
}
\end{table}
%------------------------------------------------------------------------------
% SUBSEC: CSR
% SUBSEC: conv_regs
%------------------------------------------------------------------------------
\subsection{Control and status registers}
\label{app:memmap-csr}
\subsection{Converter board registers}
\label{app:memmap-conv-regs}
\indent Base address: 0x000
\begin{table}[h]
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x0 & BID & Board ID register \\
0x4 & SR & Status register \\
0x8 & CR & Control register \\
0x00 & BIDR & Board ID register \\
0x04 & SR & Status register \\
0x08 & CR & Control register \\
0x0c & CH1PCR & Channel 1 Pulse Counter Register \\
0x10 & CH2PCR & Channel 2 Pulse Counter Register \\
0x14 & CH3PCR & Channel 3 Pulse Counter Register \\
0x18 & CH4PCR & Channel 4 Pulse Counter Register \\
0x1c & CH5PCR & Channel 5 Pulse Counter Register \\
0x20 & CH6PCR & Channel 6 Pulse Counter Register \\
\end{tabular}
\end{table}
%------------------------------------------------------------------------------
\subsubsection{Board ID register}
\subsubsection{Board ID Register}
\label{app:memmap-bidr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
......@@ -799,11 +901,12 @@ following sections list the memory map of each peripheral.
}
%------------------------------------------------------------------------------
\subsubsection{Status register}
\subsubsection{Status Register}
\label{app:memmap-sr}
\begin{tabular}{l l c c p{.35\textwidth}}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
7..0 & FWVERS & R/O & X & Firmware version \\
7..0 & GWVERS & R/O & X & gateware version \\
15..8 & SWITCHES & R/O & X & Switch status \\
21..16 & RTM & R/O & X & RTM detection lines \\
22 & CWDTO & R/W & 0 & Communication watchdog timeout \\
......@@ -815,12 +918,12 @@ following sections list the memory map of each peripheral.
\begin{tabular}{l p{.8\textwidth}}
\textbf{Field} & \textbf{Description} \\
FWVERS & Firmware version \newline
GWVERS & Gateware version \newline
-- leftmost nibble \textit{hex value} is major release \textit{decimal value} \newline
-- rightmost nibble \textit{hex value} is minor release \textit{decimal value} \newline
e.g. \newline
0x11 -- v1.1\newline
0x1e -- v1.15 \newline
0x1e -- v1.14 \newline
0x20 -- v2.0 \newline
etc. \\
SWITCHES & Current switch status \newline
......@@ -830,7 +933,7 @@ following sections list the memory map of each peripheral.
bit 7 -- SW2.4 \newline
\textbf{1} -- switch is \textbf{OFF} \newline
\textbf{0} -- switch is \textbf{ON} \\
RTM & RTM detection lines status \newline
RTM & RTM detection lines status~\cite{rtm-det} \newline
\textbf{0} -- line active \newline
\textbf{1} -- line inactive \\
CWDTO & Communication watchdog timeout status \newline
......@@ -842,7 +945,8 @@ following sections list the memory map of each peripheral.
}
%------------------------------------------------------------------------------
\subsubsection{Control register}
\subsubsection{Control Register}
\label{app:memmap-cr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
......@@ -870,6 +974,15 @@ following sections list the memory map of each peripheral.
\end{tabular}
}
%------------------------------------------------------------------------------
\subsubsection{Channel Pulse Counter Registers}
\label{app:memmap-chpcr}
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..0 & CHxPC & R/W & 0 & Pulse counter register value\\
\end{tabular}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment