Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL Blocking - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL Blocking - Gateware
Commits
3b4a2796
Commit
3b4a2796
authored
Apr 08, 2014
by
Theodor-Adrian Stana
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Remove rtm_detector component
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
b5ff33c9
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
115 additions
and
244 deletions
+115
-244
Manifest.py
modules/Manifest.py
+1
-2
rtm_detector.vhd
modules/rtm_detector.vhd
+0
-106
conv_ttl_blo.xise
syn/Release/conv_ttl_blo.xise
+113
-116
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+1
-20
No files found.
modules/Manifest.py
View file @
3b4a2796
...
...
@@ -7,6 +7,5 @@ modules = {
}
files
=
[
"reset_gen.vhd"
,
"rtm_detector.vhd"
"reset_gen.vhd"
]
modules/rtm_detector.vhd
deleted
100644 → 0
View file @
b5ff33c9
--==============================================================================
-- CERN (BE-CO-HT)
-- Rear transition module (RTM) detector
--==============================================================================
--
-- author: Carlos Gil Soriano
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-01-09
--
-- version: 2.0
--
-- description:
--
-- This module detects the presence of rear transition module motherboards
-- (RTMMs) and piggybacks (RTMPs). Detection works by checking the RTMM and
-- RTMP input pins and these pins are pulled up on the front module. The
-- RTMM_OK and RTMP_OK ouputs are set if the corresponding inputs do not
-- yield errors. Different boards have the RTMM/P pins setup differently,
-- as outlined in the tables below:
--
-- Table 1. RTMM detection pins.
-- __________________________________________
-- | Board | RTMM[2] | RTMM[1] | RTMM[0] |
-- +-----------------------------------------+
-- | Error | '1' | '1' | '1' |
-- | RTMM_V1 | '1' | '1' | '0' |
-- | RTMM_V2 | '1' | '0' | '1' |
-- | Reserved | '1' | '0' | '0' |
-- | Reserved | '0' | '1' | '1' |
-- | Reserved | '0' | '1' | '0' |
-- | Reserved | '0' | '0' | '1' |
-- | Reserved | '0' | '0' | '0' |
-- +-----------+---------+---------+---------+
--
--
-- Table 2. RTMP detection pins.
-- _____________________________________________
-- | Board | RTMP[2] | RTMP[1] | RTMP[0] |
-- +-------------------------------------------+
-- | Error OR | '1' | '1' | '1' |
-- | Blocking_V1 | | | |
-- | RS485_V1 | '1' | '1' | '0' |
-- | -Reserved- | '1' | '0' | '1' |
-- | -Reserved- | '1' | '0' | '0' |
-- | -Reserved- | '0' | '1' | '1' |
-- | -Reserved- | '0' | '1' | '0' |
-- | -Reserved- | '0' | '0' | '1' |
-- | Error | '0' | '0' | '0' |
-- +-------------+---------+---------+---------+
--
--
-- dependencies:
-- none
--
-- references:
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-01-09 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
rtm_detector
is
port
(
rtmm_i
:
in
std_logic_vector
(
2
downto
0
);
rtmp_i
:
in
std_logic_vector
(
2
downto
0
);
rtmm_ok_o
:
out
std_logic
;
rtmp_ok_o
:
out
std_logic
);
end
entity
rtm_detector
;
architecture
behav
of
rtm_detector
is
--==============================================================================
-- architecture begin
--==============================================================================
begin
rtmm_ok_o
<=
'0'
when
(
rtmm_i
=
"111"
)
else
'1'
;
rtmp_ok_o
<=
'0'
when
(
rtmp_i
=
"111"
)
else
'1'
;
end
behav
;
--==============================================================================
-- architecture end
--==============================================================================
syn/Release/conv_ttl_blo.xise
View file @
3b4a2796
...
...
@@ -362,347 +362,344 @@
<file
xil_pn:name=
"../../modules/reset_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8"
/>
</file>
<file
xil_pn:name=
"../../modules/rtm_detector.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
10
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
9
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_moving_average.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_reset.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
20
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
19
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_word_packer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_big_adder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
8
"
/>
</file>
<file
xil_pn:name=
"../../modules/Release/conv_man_trig.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
30
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
29
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
3
"
/>
</file>
<file
xil_pn:name=
"../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"3
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
40
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
39
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"4
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
50
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
49
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"5
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
60
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
59
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"6
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
70
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
69
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"7
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
80
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
79
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"8
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
90
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
89
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
100
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
99
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"10
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
10
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
09
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
0
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"11
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
20
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
19
"
/>
</file>
<file
xil_pn:name=
"../../top/Release/conv_ttl_blo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
0
"
/>
</file>
<file
xil_pn:name=
"../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"12
1
"
/>
</file>
</files>
...
...
top/Release/conv_ttl_blo.vhd
View file @
3b4a2796
...
...
@@ -587,10 +587,6 @@ architecture behav of conv_ttl_blo is
signal
rst_fr_reg
:
std_logic
;
signal
rst_125_n
:
std_logic
;
-- RTM detection signals
signal
rtmm
,
rtmp
:
std_logic_vector
(
2
downto
0
);
signal
rtmm_ok
,
rtmp_ok
:
std_logic
;
-- Wishbone crossbar signals
signal
xbar_slave_in
:
t_wishbone_slave_in_array
(
c_nr_masters
-
1
downto
0
);
signal
xbar_slave_out
:
t_wishbone_slave_out_array
(
c_nr_masters
-
1
downto
0
);
...
...
@@ -891,7 +887,7 @@ begin
--============================================================================
-- Set SWITCH and RTM fields
switches_n
<=
ttl_switch_n_i
&
extra_switch_n_i
(
7
downto
1
);
rtm_lines
<=
rtmp
&
rtmm
;
rtm_lines
<=
(
not
fpga_rtmp_n_i
)
&
(
not
fpga_rtmm_n_i
)
;
-- Then, instantiate the component
cmp_conv_regs
:
conv_regs
...
...
@@ -1462,21 +1458,6 @@ begin
line_oen_o
(
1
)
=>
led_ctrl1_oen_o
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm
<=
not
fpga_rtmm_n_i
;
rtmp
<=
not
fpga_rtmp_n_i
;
cmp_rtm_detector
:
rtm_detector
port
map
(
rtmm_i
=>
rtmm
,
rtmp_i
=>
rtmp
,
rtmm_ok_o
=>
rtmm_ok
,
rtmp_ok_o
=>
rtmp_ok
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment
Theodor Stana <t.stana@cern.ch>
Theodor Stana <t.stana@cern.ch>