Commit 2679be0d authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

removed old directories and binary files

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent a7899fb2
This diff is collapsed.
This diff is collapsed.
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:55:00 04/04/2012
-- Design Name: CONV_TTL_BLO image 0
-- Module Name: image0_top - Behavioral
-- Project Name: CONV_TTL_BLO
-- Target Devices: Spartan 6 SLX45T
-- Tool versions:
-- Description: image0_top.vhd comprises the integration of four vhdl modules:
-- 1.- Trigger
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity image0_top is
generic(
g_NUMBER_OF_CHANNELS : INTEGER := 6
);
port(
LED_SYS_PW : out STD_LOGIC;
LED_SYS_ERROR : out STD_LOGIC;
LED_TTL : out STD_LOGIC;
LED_LINK_UP : out STD_LOGIC;
LED_PPS : out STD_LOGIC;
LED_WR_OK : out STD_LOGIC;
---------------------------------------
-- EXTRA_SWITCH
--
-- 1 rst
-- 2 general OE and TTL
-- 3 OE blocking
--------------------------------------
EXTRA_SWITCH : in STD_LOGIC_VECTOR(3 downto 1);
TTL : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC;
FPGA_OE : out STD_LOGIC;
FPGA_BLO_OE : out STD_LOGIC;
FPGA_TRIG_TTL_OE : out STD_LOGIC;
FPGA_INV_OE : out STD_LOGIC;
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_REAR_LED : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_INPUT_TTL : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
PULSE_FRONT_LED : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
FPGA_HEADER_OUT : out STD_LOGIC_VECTOR(6 downto 1)
);
end image0_top;
architecture Behavioral of image0_top is
component trigger_top is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
led_o : out STD_LOGIC;
utc_i : in STD_LOGIC_VECTOR(95 downto 0);
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR(2 downto 0)
);
end component;
signal s_wb_ack_o : STD_LOGIC;
signal s_wb_err_o : STD_LOGIC;
signal s_wb_rty_o : STD_LOGIC;
signal s_wb_data_o : STD_LOGIC_VECTOR(31 downto 0);
signal s_PULSE_FRONT_LED : STD_LOGIC_VECTOR(6 downto 1);
signal s_FPGA_INPUT_TTL : STD_LOGIC_VECTOR(6 downto 1);
signal s_pulse_i : STD_LOGIC_VECTOR(6 downto 1);
signal s_pulse_o : STD_LOGIC_VECTOR(6 downto 1);
signal s_led_o : STD_LOGIC_VECTOR(6 downto 1);
signal clock_n : STD_LOGIC;
begin
-- IO Logic is inverted
LED_SYS_PW <= '0';
LED_SYS_ERROR <= '1';
LED_TTL <= '1';
LED_LINK_UP <= '1' ;
LED_PPS <= '1' ;
LED_WR_OK <= '1' ;
FPGA_INV_OE <= '0';
-- This assignments have not to be clocked
FPGA_TRIG_BLO <= s_pulse_o;
PULSE_REAR_LED <= not(s_led_o);
s_pulse_i <= not(FPGA_INPUT_TTL);
FPGA_OUT_TTL <= s_pulse_o;
PULSE_FRONT_LED <= not(s_led_o);
-- INV_OUT(1) <= CLK20_VCXO;
INV_OUT(4 downto 1) <= (others => '1');
FPGA_HEADER_OUT <= (others => '1');
trigger_channels_loop: for i in 0 to g_NUMBER_OF_CHANNELS - 1 generate
begin
trigger_inst: trigger_top
port map(
pulse_i => s_pulse_i (1+i),
pulse_o => s_pulse_o (1+i),
led_o => s_led_o (1+i),
utc_i => (others => '0'),
wb_rst_i => EXTRA_SWITCH(1),
wb_clk => CLK20_VCXO,
wb_stb_i => '0',
wb_cyc_i => '0',
wb_ack_o => s_wb_ack_o,
wb_err_o => s_wb_err_o,
wb_rty_o => s_wb_rty_o,
wb_we_i => '0',
wb_sel_i => (others => '0'),
wb_data_i => (others => '0'),
wb_data_o => s_wb_data_o,
-- TODO: possibleslave_ to leave only one common wb_addr_s
wb_addr_i => (others => '0')
);
end generate trigger_channels_loop;
ttl_out: process (CLK20_VCXO)
begin
if rising_edge (CLK20_VCXO) then
if EXTRA_SWITCH(2) = '1' then
FPGA_OE <= '0';
FPGA_TRIG_TTL_OE <= '0';
else
FPGA_OE <= '1';
FPGA_TRIG_TTL_OE <= '1';
end if;
else
end if;
end process;
blo_out: process(CLK20_VCXO)
begin
if rising_edge (CLK20_VCXO) then
if EXTRA_SWITCH(3) = '1' then
FPGA_BLO_OE <= '1';
else
FPGA_BLO_OE <= '0';
end if;
else
end if;
end process;
end Behavioral;
-- testbench template
library IEEE;
use IEEE.STD_LOGIC_1164.ALl;
use IEEE.NUMERIC_STD.ALL;
entity image0_top_tb is
end image0_top_tb;
architecture Behavior of image0_top_tb is
-- component declaration
component image0_top
port(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
pulse_i : in STD_LOGIC_VECTOR(5 downto 0)
pulse_o : out STD_LOGIC_VECTOR(5 downto 0)
);
end component;
constant wb_clk_period : TIME = 50 ns;
signal rst_i : STD_LOGIC;
signal clk_i : STD_LOGIC;
signal pulse_i : STD_LOGIC_VECTOR(5 downto 0);
signal pulse_o : STD_LOGIC_VECTOR(5 downto 0);
begin
-- component instantiation
image0_top_uut: image0_top
port map(
rst_i => rst_i ,
clk_i => clk_i ,
pulse_i => pulse_i,
pulse_o => pulse_o
);
wb_clk_proc: process
begin
clk_i <= '1';
wait for wb_clk_period;
clk_i <= '0';
wait for wb_clk_period;
end process;
tb_proc: process
procedure rst_sync(lenght: TIME)
begin
wait until rising_edge(clk_i);
rst_i <= '1';
wait for 100000*wb_clk_period; -- 50ms
rst_i <= '0';
end procedure;
procedure rst_async(t0: TIME; lenght: TIME)
begin
end procedure;
procedure pulse(channel: INTEGER; lenght:TIME)
begin
wait until rising_edge(wb_clk_i);
pulse_i(channel) <= '1';
wait for lenght;
pulse_i(channel) <= '0';
end procedure;
begin
rst_sync;
-------------------------------------------------------------------------
-- Pulse should be reproduced with a value of 1.5us which equals
-- 30 wb_ck_period clocks. Then, another pulse_lenght time slot, the
-- triggers will be forbidden to reproduce pulses for safety reasons.
-- A default current glitch mask of "111111" (six wb_clk_period, 300 ns)
-- is set.
--
--------------------------------
-- INPUT PULSES TESTS
-- INPUT OUTPUT
-- 1.- Normal operation: 20 wb_clk_period 1 pulse
-- 2.- Testing antiglitch 5 wb_clk_period 0 pulses
-- 3.- Testing long pulses 59 wb_clk_period 1 pulse
-- 60 wb_clk_period 2 pulses?
-- 61 wb_clk_period 2 pulses
--------------------------------
-------------------------------------------------------------------------
pulse(1, 20 * wb_clk_period);
wait for 10 * wb_clk_period;
pulse(1, 5 * wb_clk_period);
wait for 10 * wb_clk_period;
pulse(1, 59 * wb_clk_period);
wait for 10 * wb_clk_period;
pulse(1, 60 * wb_clk_period);
wait for 10 * wb_clk_period;
pulse(1, 61 * wb_clk_period);
wait for 10 * wb_clk_period;
end process;
end;
#Ignore LaTeX trash
#doc/.*
#doc/.*_*
#doc/*.*
#doc/.*.*.swp
#doc/.*.*.swp
#doc/Figures/*.eps
#!doc/*.tex
#!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
# !project/image1.gise
!project/image1.xise
!project/image1.tcl
#!project/waveform/
# Ignore PlanAhead outputs
# *.data/*
# *.runs/*
# *.cache/*
# *.wlf
# *.jou
# *.log
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
rtl/.swo
rtl/.swp
test/.swo
test/.swp
test/.*.*.swo
test/.*.*.swp
#Ignore LaTeX trash
#doc/.*
#doc/.*_*
#doc/*.*
#doc/.*.*.swp
#doc/.*.*.swp
#doc/Figures/*.eps
#!doc/*.tex
#!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/image1.gise
!project/image1.xise
!project/image1.tcl
#!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
rtl/.swo
rtl/.swp
test/.swo
test/.swp
test/.*.*.swo
test/.*.*.swp
#! /bin/bash
echo "Running ./project/image1.tcl script to rebuild project"
echo "Log files can be found in ./build_reports"
BUILD_DIR="./project/reports/trash"
BITSTREAM_DIR="./project/bitstream"
echo "Cleaning-up eventually ISE temporary files"
rm -r ./project/iseconfig
rm -r ./project/_xmsgs
if [ ! -d "$BUILD_DIR" ]; then
echo "Creating not previously existing $BUILD_DIR"
mkdir -p $BUILD_DIR
fi
if [ ! -d "$BITSTREAM_DIR" ]; then
echo "Creating not previously existing $BITSTREAM_DIR"
mkdir -p $BITSTREAM_DIR
fi
cd $BUILD_DIR
echo "Executig tcl script from project folder"
pwd
xtclsh ../../image1.tcl rebuild_project
wait
echo "Log files are available"
cp image1_top.bld ../ngd.log &
cp image1_top.syr ../synthesis.log &
cp image1_top_summary.html ../summary.html
cd ../../..
#echo "Updating bitstream"
#cp $BUILD_DIR $BITSTREAM_DIR
##echo "Removing trash folder"
##rm -r $BUILD_DIR
This diff is collapsed.
This diff is collapsed.
NetIC14_C3
NetIC14_Y4
SFP_VCCT
SFP_VCCR
P1V2
P3V3
NetIC14_E9
FPGA_MGTAVCC
This diff is collapsed.
#!/usr/bin/python
## @package net2ucf.py
# @author Matthieu Cattin, Carlos Gil Soriano.
# This is a modified net2ucf.py by Carlos Gil Soriano,
# previously done by Matthieu Cattin.
import re
## @class net2ucf class able to extract ucf files from an Altium NET files
class NET2UCF:
## @brief Constructor of the ucf extractor
# @param path_ucfFile Path to be written the ucf file
# @param path_excludedNetsFile A path with the nets files to be excluded
# @param ICid IC identificator to extract the ucf from
def __init__(self, path_netFile, path_ucfFile, path_excludedNetsFile, ICid):
if path_netFile.endswith('.NET'):
try:
self.netFile = open(path_netFile, "r")
except IOError as e:
print '.NET file does not exist!'
else:
raise Exception('Bad extension of the net file')
if path_ucfFile.endswith('.ucf'):
try:
self.ucfFile = open(path_ucfFile, "w")
except IOError as e:
print '.ucf file does not exist!'
else:
raise Exception('Bad extension of the ucf file')
if path_excludedNetsFile.endswith('.XNET'):
try:
self.excludedNetsFile = open(path_excludedNetsFile, "r")
except IOError as e:
print '.XNET file does not exist!'
print "I'm here!"
self.listExcludedNets = []
for line in self.excludedNetsFile:
ln = line.split()
self.listExcludedNets.append(ln[0])
print 'Excluded nets:\n' + str(self.listExcludedNets)
else:
raise Exception('Bad extension of the excluded nets file')
self.ICid = ICid
## @fn generateUCF(self)
# @brief Function that process the NET file and generates the UCF one.
def generateUCF(self):
for line in self.netFile:
ln = line.split()
skip = False
for item in self.listExcludedNets:
if ln[0].startswith(str(item)):
print str(ln[0])+'Omitted because is a excluded net'
skip = True
if skip == False:
try:
print ln;
if ln[1].startswith('IC14'):
self.ucfFile.write("NET \""+ln[0]+"\" LOC = "+ln[1].split('-')[1]+";\n")
except IOError as e:
print 'Bad line in FPGA.NET'
print '-------------------------------------'
print '-------- NET2UCF program --------'
print '-------------------------------------\n'
print 'Case sensitive!\n'
path_NetFile = raw_input('Insert the path of the NET file. Format is \n'+'-- [PATH]/[name].NET:\t')
path_ucfFile = raw_input('Insert path of the ucf file. Format is \n'+'-- [PATH]/[name].ucf:\t')
path_excludedNetsFile = raw_input('Insert path of the file containing nets not to be included'+ '-- [PATH]/[name].XNET:\t')
ICid = raw_input('Insert which IC to get the ucf file from:\t')
net2ucf_inst = NET2UCF(path_NetFile, path_ucfFile, path_excludedNetsFile, ICid)
net2ucf_inst.generateUCF()
This diff is collapsed.
This diff is collapsed.
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider image1_top
add wave -noupdate /image1_top_tb/s_rst_SYS_A
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_led
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_i
add wave -noupdate -group {Front Panel} /image1_top_tb/s_pulse_o
add wave -noupdate -group {Front Panel} /image1_top_tb/s_inv_i
add wave -noupdate -group {Front Panel} /image1_top_tb/s_inv_o
add wave -noupdate -group I2C /image1_top_tb/s_sda_slave_oen
add wave -noupdate -group I2C /image1_top_tb/s_scl_slave_oen
add wave -noupdate -group I2C /image1_top_tb/s_I2C_slave_i
add wave -noupdate -group I2C /image1_top_tb/s_I2C_slave_o
add wave -noupdate -group I2C /image1_top_tb/s_FPGA_GA
add wave -noupdate -group I2C /image1_top_tb/s_FPGA_GAP
add wave -noupdate -group SPI /image1_top_tb/s_SPI_master_i
add wave -noupdate -group SPI -expand /image1_top_tb/s_SPI_master_o
add wave -noupdate -group CTRL /image1_top_tb/s_fpga_en
add wave -noupdate -group CTRL /image1_top_tb/level
add wave -noupdate -group CTRL /image1_top_tb/switch_i
add wave -noupdate -group CTRL /image1_top_tb/s_RTM_id_i
add wave -noupdate -group CTRL /image1_top_tb/manual_rst_n_o
add wave -noupdate -radix hexadecimal /image1_top_tb/s_i2c_addr_op
add wave -noupdate -divider {Status LEDs}
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_bicolor_led_ctrl/rst_n_i
add wave -noupdate /image1_top_tb/uut/CLK20_VCXO
add wave -noupdate /image1_top_tb/uut/inst_image1_core/led_array_o
add wave -noupdate /image1_top_tb/uut/inst_image1_core/s_led_state_array
add wave -noupdate -expand /image1_top_tb/uut/inst_image1_core/s_leds_array_image1
add wave -noupdate -divider wb_xbar
add wave -noupdate /image1_top_tb/wb_clk
add wave -noupdate -group wb_slave_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/slave_i
add wave -noupdate -group wb_slave_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/slave_o
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_i
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_o
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_ie
add wave -noupdate -group wb_master_xbar -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_wb_crossbar/master_oe
add wave -noupdate -divider i2c_slave
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm
add wave -noupdate /image1_top_tb/s_I2C_regs
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_ack_i
add wave -noupdate -group wb_master -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_addr_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_cyc_o
add wave -noupdate -group wb_master -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_data_i
add wave -noupdate -group wb_master -radix hexadecimal /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_data_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_err_i
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_rty_i
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_sel_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_stb_o
add wave -noupdate -group wb_master /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_master_we_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_ack_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_addr_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_cyc_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_data_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_data_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_err_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_rty_o
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_sel_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_stb_i
add wave -noupdate -group wb_slave_i2c /image1_top_tb/uut/inst_image1_core/inst_i2c_slave/wb_slave_we_i
add wave -noupdate -divider m25p32
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_m25p32/inst_m25p32_core/s_MEM_fsm
add wave -noupdate /image1_top_tb/s_M25P32_regs
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_we_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_stb_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_sel_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_rty_o
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_rst_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_err_o
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_data_o
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_data_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_cyc_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_clk
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_addr_i
add wave -noupdate -group wb_slave_m25p32 /image1_top_tb/uut/inst_image1_core/inst_m25p32/wb_ack_o
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/rd_data_o
add wave -noupdate -divider multiboot
add wave -noupdate /image1_top_tb/uut/inst_image1_core/inst_multiboot/multiboot_core_inst/s_ICAP_fsm
add wave -noupdate /image1_top_tb/s_MULTIBOOT_regs
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_we_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_stb_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_sel_i
add wave -noupdate -group wb_slave_multiboot /image1_top_tb/uut/inst_image1_core/inst_multiboot/wb_rty_o