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Conv TTL Blocking - Gateware
Commit 24c4474d authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Added multiboot module documentation 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 00356b8c
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doc/multiboot/Makefile 0 → 100644
View file @ 24c4474d
FILE=multiboot
all:
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
doc/multiboot/cern-title.tex 0 → 100644
View file @ 24c4474d
\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{Xilinx MultiBoot module}}
\noindent \rule{\textwidth}{.1cm}
\hfill\today
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
doc/multiboot/fig/fsm.svg 0 → 100644
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doc/multiboot/fig/multiple-spi.svg 0 → 100644
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doc/multiboot/fig/spi-mode.svg 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
doc/multiboot/multiboot.bib 0 → 100644
View file @ 24c4474d
@misc{ohwr,
title = {{Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/}}
}
@misc{ug380,
title = {{UG380 - Spartan-6 Configuration Guide}},
author = {Xilinx},
month = jan,
year = {2013},
note = {v2.5},
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{xtp059,
title = {{XTP059: SP605 MultiBoot Design}},
howpublished = {\url{http://www.xilinx.com/support/documentation/boards_and_kits/xtp059.pdf}},
urldate = {2013-10-25},
publisher = {Dec. 2009},
author = {Xilinx},
file = {XTP059: SP605 MultiBoot Design}
}
@misc{xil-multiboot-ohwr,
title = {{Xilinx MultiBoot module Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo-gw/wiki/Xil_multiboot}},
urldate = {2013-10-25},
author = {Stana, Theodor-Adrian},
month = oct,
year = {2013}
}
@misc{gen-bitstream,
title = {{Generating Bitstreams for MultiBoot designs (Xilinx MultiBoot module Project Page on OHWR)}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo-gw/wiki/Xil_multiboot#Generating-bitstreams-for-Xilinx-FPGA-reprogramming}},
urldate = {2013-10-25},
author = {Stana, Theodor-Adrian},
month = oct,
year = {2013}
}
@misc{gencores-ohwr,
title = {{Generic Cores Library OHWR Project Page}},
howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
}
@misc{ctb-proj,
title = {{CONV-TTL-BLO Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki}},
month = oct,
year = {2013}
}
@misc{ctb-repo,
title = {{CONV-TTL-BLO Gateware Repository on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo-gw/repository}},
month = oct,
year = {2013}
}
@misc{xil-devref,
title = {{Xilinx Command Line Tools User Guide (UG628)}},
howpublished = {\url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/devref.pdf}},
author = {Xilinx},
month = jul,
year = {2012}
}
doc/multiboot/multiboot.tex 0 → 100644
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hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ 24c4474d
......@@ -361,12 +361,12 @@ begin
-- RDCFGREG read sequence
-- as per Table 6-1, p.113 [1], starting from step 6
--====================================================================
-- write type1 packet header to read RDCFGREG register
-- write type1 packet header to read CFGREGADR register
-- (packet headers can be found on page 93 of [1])
when RDCFGREG_CMD =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
icap_dat_o <= "001" & "01" & reg_cfgregadr_i & "00001"; --x"2c01";
icap_dat_o <= "001" & "01" & reg_cfgregadr_i & "00001";
state <= RDCFGREG_NOOP_1;
-- then four noops
......
hdl/multiboot/syn/conv_ttl_blo.gise deleted 100644 → 0
View file @ 00356b8c
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="conv_ttl_blo.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="conv_ttl_blo.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="conv_ttl_blo.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087311" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1382087311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087321" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382087311">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.lso"/>
<outfile xil_pn:name="conv_ttl_blo.prj"/>
<outfile xil_pn:name="conv_ttl_blo.syr"/>
<outfile xil_pn:name="conv_ttl_blo.xst"/>
<outfile xil_pn:name="conv_ttl_blo_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1382087321" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1382087321">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
hdl/multiboot/syn/run.tcl deleted 100644 → 0
View file @ 00356b8c
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
hdl/release/syn/conv_ttl_blo.gise
View file @ 24c4474d
......@@ -75,35 +75,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1382087370">
<transform xil_pn:end_ts="1382973055" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1382973055">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1382087370">
<transform xil_pn:end_ts="1382973055" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1382973055">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1382087370">
<transform xil_pn:end_ts="1382973055" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1382973055">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1382087370">
<transform xil_pn:end_ts="1382973055" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1382973055">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1382087370">
<transform xil_pn:end_ts="1382973055" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1382973055">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1382087370">
<transform xil_pn:end_ts="1382973055" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1382973055">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382087370" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1382087370">
<transform xil_pn:end_ts="1382973055" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1382973055">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382450222" xil_pn:in_ck="3190287689474023470" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382450200">
<transform xil_pn:end_ts="1382974467" xil_pn:in_ck="3190287689474023470" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1382974444">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -121,11 +121,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1382087394" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1382087394">
<transform xil_pn:end_ts="1382973080" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1382973080">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1382450228" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1382450222">
<transform xil_pn:end_ts="1382974475" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1382974467">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -134,11 +134,9 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1382450282" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1382450228">
<transform xil_pn:end_ts="1382974529" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-3650938198851982977" xil_pn:start_ts="1382974475">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_map.map"/>
......@@ -149,7 +147,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1382450332" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1382450282">
<transform xil_pn:end_ts="1382974581" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1382974529">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -164,7 +162,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1382450366" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-3614567692198564809" xil_pn:start_ts="1382450332">
<transform xil_pn:end_ts="1382974615" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-3614567692198564809" xil_pn:start_ts="1382974581">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -177,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1382450332" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1382450324">
<transform xil_pn:end_ts="1382974581" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1382974571">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo.xise
View file @ 24c4474d
......@@ -111,7 +111,7 @@
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
......
hdl/release/top/conv_ttl_blo.vhd
View file @ 24c4474d
......@@ -445,7 +445,7 @@ begin
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb
cmp_vbcp_bridge : vbcp_wb
port map
(
-- Clock, reset
......@@ -794,7 +794,7 @@ begin
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrli : bicolor_led_ctrl
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
......
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